Browse Prior Art Database

Radiation Hardening for analog reference voltage node

IP.com Disclosure Number: IPCOM000201799D
Publication Date: 2010-Nov-23
Document File: 5 page(s) / 198K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method to mitigate the amplitude and the duration of disturbance caused by radiation hit on an analog reference voltage node is described.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 56% of the total text.

Page 01 of 5

A method to mitigate the amplitude and the duration of disturbance caused by radiation hit on an analog reference voltage node is described. The proposed idea effectively reduces the radiation hit impact to the analog node. In comparison to the conventional bypass capacitor approach, this implementation uses a much smaller silicon area and also has better radiation hit immunity. Coupling capacitance and negative feedback techniques are used in this circuit to achieve these results. Simulation waveforms comparing this solution to uncompensated loading as well to the conventional bypass capacitor scheme are shown in the diagrams and Figures 1-5 below.

1. General Block Diagram

(This page contains 00 pictures or other non-text object)

Where:
- Vanalog : The analog node to be hardened
- Ihit : Radiation hit current
- G(S) : The transfer function from the current to voltage at node v analog
- Gc(S) : Transfer function from v analog to the compensation current Icomp
- Icomp : The compensation current : Icomp(S) = vanalog * Gc(S)
- Ipure : The summation of the hit current and the compensation current

The relationship :

Icomp= Gc(S) * Vanalog
Ipure = Ihit - Icomp
Vanalog = Ipure(S) * G(S)

Block Diagram

(This page contains 01 pictures or other non-text object)

Conventional Bypass Scheme illustration

1


Page 02 of 5

(This page contains 00 pictures or other non-text object)

The Innovation Circuit

(This page contains 01 pictures or other non-text object)


2. Simulation Analysis:

Radiatio...