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A Novel Approach to Enhance Test Coverage using Existing Boundary Scan Cells

IP.com Disclosure Number: IPCOM000201875D
Publication Date: 2010-Nov-29
Document File: 5 page(s) / 292K

Publishing Venue

The IP.com Prior Art Database

Abstract

This document describes an innovative and efficient way to achieve high test coverage on SoC pin muxing/interface logic without impacting the die size or the test cost. The method proposed uses existing SoC logic to detect faults on pin muxing as opposed to conventional method where either test logic is inserted or the entire SoC pins are brought in contact on tester. The solution provided is very generic which can be used across SoC with simple automation.

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A Novel Approach to Enhance Test Coverage using Existing Boundary Scan Cells

Abstract

This document describes an innovative and efficient way to achieve high test coverage on SoC pin muxing/interface logic without impacting the die size or the test cost. The method proposed uses existing SoC logic to detect faults on pin muxing as opposed to conventional method where either test logic is inserted or the entire SoC pins are brought in contact on tester.  The solution provided is very generic which can be used across SoC with simple automation.

Problem Statement

In high pin package SoC designs, the amount of stuck-at faults on the I/O pad and its muxing logic is very significant. To achieve 99+% stuck-at test coverage goal on SoC, the faults on I/O pad logic are either detected by inserting huge number of test points in the pin muxing logic or by bringing all the SoC pins in contact on the tester. Both of these methods lead to increased cost either in terms of large die size or reduced multisite testing of SoC on tester. Methods which have been followed in most of the SoC designs so far:

1. Scan Observability by adding test point register on pin muxing

In the current pin muxing architecture, to observe the pad control signals (like ibe, obe, pue)  and pad electrical signals (like dse, sre, hys), a test point register (TPR) is added corresponding to each pad. These pad electrical signals and control signals are ex-ored and observed in the test point  register (TPR). Thereby, leads to the addition of TPR  equal to  p x number of digital pads in the SoC, where p is the number of TPR used against each pad.

2Scan observability by observing all the pins on tester

The second option which is less adopted is to observe the data-out on the pads itself by keeping all the pads/pins in contact on tester. This method reduces the number of SoCs that can be tested in parallel on tester simultaneously, thereby leading to high test cost. Beside increased test cost, the test coverage achieved on pads is not high as pad electrical controls (like sre, hys, dse) can not be detected using this method.

There were two reasons behind this innovation:

1. Achieving high test coverage on pin muxing with reduced test logic

2. Achieving high test coverage on pin muxing with reduced pin count in contact on tester

Solution :: Method

To achieve high stuck-at coverage on pin muxing logic without inserting test point registers, and keeping minimal pins in contact on tester. We propose to use the existing BSR flops in the design to observe faults on the pad electrical and control signals. Using any functional flop of the design will require detailed analysis to figure out the impact on functional timing and huge manual efforts required to integrate it individually on each pad. Therefore, the idea is to use the BSR flops having no impact on timing as the clock frequency is very slow on the JTAG interface. Moreover, the BSR flops are present uniformly across all the digital...