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Method and Apparatus of Bus Routing Aware Chip Sizing

IP.com Disclosure Number: IPCOM000202016D
Publication Date: 2010-Dec-01
Document File: 7 page(s) / 157K

Publishing Venue

The IP.com Prior Art Database

Abstract

Abstract: For most of hierarchical chip, wiring resource in top-level becomes the bottleneck of chip size. Disclosed is a method developed to get more accurate chip size, by involving the impact of bus routing in top-level.

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Method and Apparatus of Bus Routing Aware Chip Sizing

Chip sizing is one of the most important steps in early stage of ASIC business bidding and chip design. Usually, a smaller chip means lower cost therefore is more competitive for business, but it also means a higher technical implementation risk because the chip is more dense and congested. Therefore, making the sizing more accurate is the key point to trade off the cost and risk , and to make the chip solution more competitive in the market .

Generally speaking, traditional solution of chip sizing is a density-based method. Experience based highest cell density is set to be the target of chip, then the chip size could be calculated by the total area of cells being divided by the target density .

The density-based sizing method works well for mostof traditional chips, because in these chips, the area of macros and standard cells are roughly equal, and most nets are evenly distributed on the chip. And the wire resource isn't the bottle neck to decide the chip size. Therefore taking cell density as the only factor is enough for sizing. But with the quick scale and complexity increase of ASIC design, more and more designs employ hierarchical design methodology to reduce design complexity and shorten turn-around-time. In such a hierarchical chip, hardmacros and RLMs (designer customized macros) play different functions and then they are connected by wide buses on top-level, to make up a full chip.

In such an application, typically the area occupied by macros (and RLMs) are much bigger than standard cells (glue logic) on chip top-level, because the main function are already implemented inside of RLM and hard macro, top-level only takes the role of bus connection and configuration. The context change makes it possible that bus routability become the bottle neck to decide the chip size .

We found the traditional density based sizing method shows more and more inaccuracy because it takes the density the only factor to size the chip, and doesn't consider the scenario of connection.

For example,

we have two designs,

                                        and they have the similar size macros (or RLMs for hierarchical design) but different connections. Both designs are made up mainly by big macros or RLMs, and the glue logic area on top is very few. With the traditional density based sizing method , they will be estimated to have similar chip size.

_0

Design

and Design

_1,

1



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X X

X X

A

B

C

A

B

C

Y Y

Y

F

E

D

D esign_0

Y

Y

F

E

D

Design_1

Y

X

X

X

X

Fig. 1 - Design

_0 (Simple Connection Chip

) Fig. 2- Design

_1 (Complex Connection Chip)

            the distance between macros could be almost ZERO, because all connections are between neighbor macros, there's no net or bus travel through the channel between macros. Therefore,

X and Y distance marked in the figure could be very small

But for Design

_0,

.

              Buses have to travel though the channel between macros, the distance between macros needs to be big enough to accommodate the buse...