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A Optimization Method of Priority Multiplexer under Logic Synthesis Process

IP.com Disclosure Number: IPCOM000202017D
Publication Date: 2010-Dec-01
Document File: 6 page(s) / 130K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention provides a method to optimize the speed of priority multiplexer structure while logic synthesis, including: distinguishing the switch for optimization in pre-operation stage; parsing the IF-ELSE syntax described priority multiplexer structure in HDL design; building the library of parallel circuits, and mapping the priority multiplexer structure to parallel circuit. This invention can optimize the speed of priority multiplexer structure with the cost of area.

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A Optimization Method of Priority Multiplexer under Logic Synthesis Process

Digital integrated circuit design methodology is experienced decades of development, from the evolution of the full custom development to using hardware description language (HDL) and electronic design automation tool (EDA). Hardware description language is a kind of language to describe the digital circuit and system with formal methods. Circuit designer can use HDL to describe the design thought from the concrete to the abstract, and model the digital system with a series of hierarchical model. Circuit designer need to convert the HDL to gate-level netlist with the logic synthesis tools, do floorplan, placement and routing on the netlist, generate the circuit layout to manufacture.

Logic synthesis is a process to convert HDL design to gate-level netlist and optimize the speed, area and power of the design based on standard cell library and specific constraints. Standard cell library contains simple design element, for example, OR-gate, AND-gate, XOR-gate, and common used macro like adder, multiplexer, scan-registers. Circuit designer must constraint the speed, area and power of the design, to make the logic synthesis tools work under specific design constraint.

Priority multiplexer structure is a common used circuit in integrated circuit, can be described as IF-ELSE syntax with HDL, and is presented as a serial of 2to1 multiplexer after logic synthesis process. Electrical signal takes long time to transfer through a serial of 2to1 multiplexer, and the design can't meet the speed constraint if the constraint is strict. This invention provide a method to optimize the speed of priority multiplexer structure under logic synthesis process.

This invention provides a method to optimize the speed of priority multiplexer structure while logic synthesis, including: distinguishing the switch for optimization in pre-operation stage; parsing the IF-ELSE syntax described priority multiplexer structure in HDL design; building the library of parallel circuits, and mapping the priority multiplexer structure to parallel circuit. This invention can optimize the speed of priority multiplexer structure with the cost of area.

Below we will provide the detail description of the method to optimize the speed of priority multiplexer structure while logic synthesis.

Figure 1 is the flow chart of the method to optimize priority multiplexer structure in this invention, and an overview of the concrete implementation process.

The optimization method in this invention starts from step 110. Circuit designer will set the target frequency, area and power of current design, constraint the special data path before start logic synthesis. In step 110, circuit designer need to determine whether to optimize the priority multiplexer structure with the method provided in this invention, and set the related switch parameter in the constraint file. If current design is an integrated circuit with l...