Browse Prior Art Database

Fast address generation

IP.com Disclosure Number: IPCOM000202022D
Publication Date: 2010-Dec-01
Document File: 6 page(s) / 121K

Publishing Venue

The IP.com Prior Art Database

Abstract

The proposed implementation described here uses two sets of counters. One of the counters always counts “one” ahead of the other counter. When an acknowledgment is received, the output of the counter that is “one” ahead of the other is selected, otherwise the normal counter is selected. This arrangement reduces the delay involved in generating "advance address" and works at higher frequency.

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Page 01 of 6

Fast address generation

Introduction

In many data transfer protocols, data transfer happens with the help of hand shaking signals between the two devices. For example, when device A wants to transfer the data to device B, it puts the data on the data bus and initiates transfer by activating the data-valid (Valid) signal. Once the device B reads the data, it acknowledges the read by data acknowledge (ACK) signal. Figure 1 shows the block diagram of such an implementation.

Device A

Device B

Data

Valid

ACK

Figure 1: Data transfer between two devices using hand-shaking signals.

Once the ACK signal is activated by the device B, the device A knows that the current data has been read by the device B and ready to accept the new data. If there is immediate data available with device A, it can transfer it with the help of "valid" signal.

In most of data transfer implementations it so happens that the device A has to read the valid acknowledgment from the device B before it can put the new data. This kind of an arrangement needs at least one clock cycle to read the acknowledgment and put the new data. In this way there is an extra clock cycle for every data cycle. This
is explained in timing diagram of Figure 2 below.

Data

Data 1

Data 2

Data 3

Valid

ACK

 Mem ADDR

Valid

Valid

Valid

ACK

ACK

ACK

ADDR1

ADDR2

ADDR3

ADDR4

1


Page 02 of 6

Figure 2: Timing diagram showing data transfer.

Referring to the timing diagram in Figure 2, the device A puts the data along with the valid signal. Device B read the data and in response sends an acknowledgment to the device A.

The device A reads the acknowledgment. Increments the memory address in the next clock cycle to get the next data. As the data is stored in the memory device, many of the memory devices need one clock cycle to put the new data when address changes. This is shown in the timing diagram above. So to validate the next data, there is a need of one extra clock cycle. Effectively, for every data transfer we need 2 clock cycles. This will slow down the system performance.

In a conventional method, to reduce the latency, the acknowledgment signal is used to generate the address of the next data in advance, i.e. along with the acknowledgment signal. With this arrangement one can get the valid data in every clock cycle. Figure 3 shows the timing diagram for getting the data in every clock cycle.

Data

Valid

ACK

 Mem ADDR

Figure 3: Generation of address in advance when acknowledgment is received.

Comparing Figure 2 and Figure 3, it is clear that in Figure 2 that if there is an acknowledgment in the current cycle the corresponding new address is generated in the next cycle. This is because reading an acknowledgment and then updating the address takes one clock cycle. In Figure 3, the new address is generated along with the acknowledgment. Looking at Figure 2 and Figure 3, it is clear that there is a need to generate the data every clock cycle by generating the address every clock cycle, to enhance the syst...