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Method for package connection assignment

IP.com Disclosure Number: IPCOM000202028D
Publication Date: 2010-Dec-01

Publishing Venue

The IP.com Prior Art Database

Abstract

With the development of package technology and intensive requirement for including lots of signal interfaces in a single package, It will take more and more time to assign connections from chip solder bump to package solder ball in the early stage, so the method of auto assignment for package design can save the TAT and cost of the design.The package design is always cooperated with chip design, which is so-called chip-package-co-design, the auto-assignment method can instruct chip IOs placement & evaluation soon. The auto-assignment method can decrease RATS (the connection line between solder bump and solder ball) crossing effectively and fast. The current method has some shortage in practical application, which will be introduced below, this paper will put forward a more effective method for package connection design.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 27% of the total text.

Page 01 of 16

Method for package connection assignment

     Package is key component used to connect die with PCB.The connection is to map terminals from die to PCB via metal wire among package. The mapping and assemble process is called chip packaging. The quantity of terminals continue to increase due to on-chip input and output pin counts becomes larger. Assigning terminals connections between chip solder bumps and package solder balls consumes tremendous time and resource due to above reasons.

     Auto-assignment algorithm and process was developed to help resolve those problem. Existing auto-assignment methods have some shortages, because they still need manual interaction..

     The said disclosure below,United Stated Patent Application Publication No. US 2007/7275229 B2 , titled "Auto connection assignment system and method" describes a package connection auto-assignment method.The said method includes:

1) Factor based assignment method. Factor includes signal type, package layer, escape pattern, region number etc.

2) Assignment algorithm based on sector angle as the next figure.

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Page 02 of 16

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The problems of above prior art patent include:

Miss connection assignment

  
Difficult to routine since large scale mapping wire cross (RATs: the connection line between solder bump and solder ball )

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Page 03 of 16

Can not assign power terminals

  
Hard to adjust existing assignment by group for flexible modification due to package enlarge etc
The proposed idea of our invention has following features and advantage compared to known prior art solution above :
1. It is comprehensive package connection auto-assignment method,

which ensure no missing connection.

2. The proposed solution includes IO (Input/Output buffer) power terminals assignment.
3. The proposed solution can identify RATs crossing'over and dissolve the RATs crossing.

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Page 04 of 16

Terms

Terminals

Solder bump - the metal terminal on die, used to connect die with package top.

Solder ball -- the metal terminal on package, used to connect package with PCB, usually solder ball's pitch is much larger than solder bump for easily 2nd level assemble.

The left figure shows a sketch map of a flip-chip package. The internal square indicates die outline. The external square shows a package outline. This is one top view graph

" " means the beforehand assigned solder bumps which need to be assigned with solder balls.

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Power solder ball - Unlike standard solder ball (signal solder ball), power solder balls are not 1:1 mapped with corresponding solder bump on die. All the power solder ball below to the same power net which will be routed as a chain.

Power solder bump - similar as power solder ball. Locates on die

" " means the solder bumps have been assigned with solder balls.

RTAs -- The connections between signal solder bumps and...