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Structure to eliminate preheat to all electronic nodes in a Data Center

IP.com Disclosure Number: IPCOM000202196D
Publication Date: 2010-Dec-08
Document File: 6 page(s) / 389K

Publishing Venue

The IP.com Prior Art Database

Abstract

To maximize datacenter energy efficiency, disclosed is an architecture that allows computational nodes to be cooled within a datacenter with no additional power demands beyond the actual node power requirements.

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Structure to eliminate preheat to all electronic nodes in a Data Center

It has become fairly well known that the cost of power and cooling are at the top of the list of costs for operating a data center. One way to address this at a datacenter level is the concept of Power Usage Effectiveness (PUE)[1]. This is the ratio of total data center power at the meter to the power used by the actual IT equipment. In order to improve the PUE of a data center, power distribution and data center cooling methods require new ideas to improve efficiency. One area to look at improving efficiency is to raise the ambient environmental operating conditions so that less energy for cooling would be required [2].

Often times the datacenter ambient air is preheated by components in series within a chassis that can cause the internal local ambient temperature to rise 20C or more. This can be within a server chassis or within a larger facility (a modular data center within a shipping container). This temperature rise can make it extremely difficult to achieve reliable operating temperatures for many electronic devices. This condition can preclude raising data center ambient air temperature requirements.

The basic premise of this disclosure is that to achieve the best PUE, no power should be required for cooling the electronics. To achieve this goal, an architecture is proposed that allows each processing node to get fresh air through the use of free or natural convection. As an example, today there exist desktop machines using low power processors that are rated for 50C ambient with no fans. Our concept would be to package many nodes based on this low power design point. Figure 1is a representation of a processor node that would contain a low power processor, memory, solid state drives, and I/O. These nodes...