Method and System for Addressing a Two-Tier Memory
Publication Date: 2010-Dec-13
The IP.com Prior Art Database
A method and system for addressing a two-tier memory is disclosed. The two-tier memory includes a flash memory and a Dynamic Random Access Memory (DRAM). As such, an instruction is used for asynchronously pre-fetching data from the flash memory into the DRAM without blocking the execution of the instruction. Thereafter, a real address space is used to support the instruction.
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Method and System for Addressing a Two -Tier Memory
Typically, latency associated with accessing a flash memory is much longer compared to that of a Dynamic Random Access Memory (DRAM). Therefore, addressing the flash memory in a real address space and issuing a load/store instruction to the flash memory may block execution of a microprocessor for a long time compared to addressing the DRAM in the real address space. In addition, current microprocessor designs do not have sufficient hardware resources, such as registers, queues and program counters etc., in order to support such a long latency of the flash memory, especially when the flash memory needs to be addressed in the real address space.
Disclosed is a method and system for addressing a two-tier memory, wherein two-tier memory includes the flash memory and the DRAM.
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The method and system for addressing the two-tier memory is exemplarily illustrated in the figure. The size of the real address space is larger than the DRAM. As such, the size of the real address space is approximately equal to the combined size of the flash memory and the DRAM. In addition, as shown in the figure, an address indirection table maps real addresses from the real address space to physical addresses in the DRAM.
Thereafter, a two-tier memory aware application, such as a flash aware application, issues a TOUCH instruction. The TOUCH instruction is a non-blocking instruction used by the flash aware application for pre-fetching data located at the address in the flash
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