Browse Prior Art Database

Method and System for Assigning Position of Ports/Cells in an Integrated Circuit (IC) Chip

IP.com Disclosure Number: IPCOM000202343D
Publication Date: 2010-Dec-14
Document File: 4 page(s) / 381K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for assigning position of ports/cells in an Integrated Circuit (IC) chip is disclosed. The method involves utilizing information pertaining to wiring blockage, relative position of ports/cells, and timing constraints from a top-level design for optimally assigning the position of ports/cells at a unit level design, wherein the unit level design is performed independent of other unit level designs.

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This is the abbreviated version, containing approximately 54% of the total text.

Page 01 of 4

Method and System for Assigning Position of Ports /Cells in an Integrated Circuit (IC)

Chip


Disclosed is a method and system for assigning position of ports/cells in an Integrated

Circuit (IC) chip. The method involves utilizing information pertaining to wiring blockage,

relative position of ports/cells, and timing constraints from a top-level design for

optimally assigning the position of ports/cells at a unit level design, wherein the unit

level design is performed independent of other unit level designs.

The method and system for assigning position of ports/cells in an Integrated Circuit (IC)

chip at a unit level design is illustrated using Fig. 1.

(This page contains 00 pictures or other non-text object)

Figure 1

As shown in Fig. 1, data corresponding to the IC chip is saved as part of a netlist data

while saving a top-level design. The top-level design is saved for a unit level macro

such as a Random Logic Macro (RLM). The top-level design saved as the part of the

netlist data may be presented in the following format: MACRO1 location1 shape1
PORT

_INFO

_

_

macro1

port1 connected

port2 connected

_cell2 20 40

_cell1 10 30

macro1

1


Page 02 of 4

macro1

_

port3 connected

_cell3 25 35

BLOCKAGE

_INFO

PC 10 22 10 24
M1 22 33 44 00
M2 22 33 99 00 99 00 44 55 M3
M4
M5
M6
M7
M8
TIMING

_INFO

macro1

_

port1 driving

_

cell1 location1 wiring

_

information1 coupling

_information1

macro1

_

port2 driving

_

cell1 location2 wiring

_

information2 coupling

_information2

macro1

_

port3 driving

_

cell1 location2 wiring

_

information3 coupling

_information3

MACRO2 location2 shape2 PORT

_INFO

macro2

_

port1 connected

_cell1 10 30

macro2

_

port2 connected

_cell2 20 40

macro2

_

port3 connected

_cell3 25 35

BLOCKAGE

_INFO

PC 10 22 10 24 M1 22 33 44 00

2


Page 03 of 4

M2 22 33 99 00 99 00 44 55 M3
M4
M5
M6
M7
M8
TIMING

_INFO

macro2

_

port1 driving

_

cell1 location1 wiring

_

information1 coupling

_information1

macro2

_

port2 driving

_

cell2 location2 wiring

_

information2 coupling

_information2

macro2

_

port3 driving

_

cell3 location3 wiring

_

information3 coupling

_information3

Upon saving the data corresponding to the IC chip, additional netlist data is saved for

each RLM. The additional netlist data includes information pertaining to wiring

blockage, relative position of ports/cells, and timing constraints for optimally assigning

the position of ports/cells at the unit level design. The timing constraints include timing

information of the cells for which the ports are connected to such as cell book type

(library information), wire connection type, wire...