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Method for Performing Timing Driven Antenna Violation Correction In Digital IC Design

IP.com Disclosure Number: IPCOM000202344D
Publication Date: 2010-Dec-14
Document File: 5 page(s) / 118K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for correcting antenna violations in high-density integrated circuits (IC). Method includes determining a gate which has a potential antenna violation. The gate is then automatically replaced by an equivalent gate of same functionality which has a wider gate area. The timing information at this gate is considered while performing this correction.

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This is the abbreviated version, containing approximately 52% of the total text.

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Method for Performing Timing Driven Antenna Violation Correction In Digital IC Design

A method is disclosed for correcting antenna violations in high-density integrated circuits (IC). Method includes determining a gate which has a potential antenna violation. The gate is then automatically replaced by an equivalent gate of same functionality which has a wider gate area. The timing information at this gate is considered while performing this correction.

Traditional design flow of designing a digital integrated circuit involves critical steps of Design Rule Check (DRC) and Layout Vs Schematic (LVS).

The LVS checks if there is a proper match between layout and schematic of the design. Any shorts or opens in the layout are checked in this step. Failure in LVS results in a non working chip.

Similarly, the DRC checks adherence of the design to foundry design rules. This contains rules such as spacing rules, width rules for the wires, density rules, and antenna rules which make the design manufactureable. Violation of these rules could result in a non working chip or a very low yield. Hence, DRC is absolutely necessary to pass for the chip to function.

The method disclosed herein is targeted towards the design rules called the antenna rule. The antenna rule checks to see if there is any charge accumulation on wires during the course of manufacturing the chip. Such charge accumulation gets discharged through the gate of a transistor that the wire is connected to (the sink). The discharge through the gate could potentially damage the gate and hence the functioning of the chip. Therefore, the DRC for antenna rule checks to see if this charge accumulation could happen and if the gate is enough to withstand this.

The figure illustrates a flow chart for checking antenna rule violations in accordance with the method disclosed herein.

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Figure

As shown in the figure, first the design is routed to produce as much as possible a DRC clean design. The DRC is now checked for any antenna violations. In step 2, the DRC is checked for antennas. If there are no antennas in the design, this is end of the flow. If the antenna violations exist, then a timing report is generated to check timing at these gates.

In step 3, the method chooses the gates or upsizes the gates which have the violation of antenna and negative slacks. This aims at improving timing and fixing antenna. The gate area is less for smaller width transistors and larger for transistors with higher widths. After the upsizing is done, the design is checked again for antenna and timing. If the antenna is fixed, then the flow ends.

Below is an exemplary report that shows the gate on which the antenna violations exists, the metal area and the gate area.

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