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Device and Method to accelerate Shmooing on a server system using Heuristic Parallel Pipelined Test

IP.com Disclosure Number: IPCOM000202386D
Publication Date: 2010-Dec-15
Document File: 7 page(s) / 412K

Publishing Venue

The IP.com Prior Art Database

Abstract

Proposed here is a control system/method that enables a System bring-up/characterization engineer to Shmoo DUTs (Device Under Test) as fast as possible by combining fast shmoo algorithms with a unique heuristic pipelined system test control method that cuts down system characterization time drastically. This enables the maximum utilization of development hardware and cuts down associate test time, hence the power and personnel involvement in a product engineering effort.

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Device and Method to accelerate Shmooing on a server system using Heuristic Parallel Pipelined Test

Disclosed is a control system/method that enables a System bring-up/characterization engineer to Shmoo DUTs (Device Under Test) as fast as possible by combining fast shmoo algorithms with a unique heuristic pipelined system test control method that cuts down system characterization time drastically. This enables the maximum utilization of development hardware and cuts down associated test time, hence the power and personnel involvement in a product engineering effort.

Background

    It is critical in any product engineering effort to characterize the performance of an electrical device with respect to functional parameters associated with the device (sometimes referred to as parametric testing). The outcome of these tests is plotted in a pass/fail (binary) or

parametric plot known as Shmoo (or Schmoo or smoo)

server system there are numerous devices that require system level characterization - memory controllers, memory DIMMs, SATA controllers,

Network controllers, PCI link controllers, SMP

Node controllers, etc. Traditionally, characterization methods follow one chip at a time testing

which leads to exponential or linear increases in runtimes and hence possibly sacrifices coverage due to limited resources at hand (Time to market , Engineers ).

Description

    Disclosed is a unique system that supports a "Heuristic Pipelined parallel DUT test" ( Figs. 1 & 2 ) which involves a set of data structures , control/search algorithm(s), interfaces to the DUT ( debug lines/SCOM/JTAG access or inband/mainline access ), a host system, and more than 1 DUT attached to the host. This method also specifies a model to predict or optimize the test runtimes on a system, hence enabling planned characterization and coverage shifts or optimum string size of DUTs. The heuristic component augments the pipelined parallel test

procedure with statistical inputs.

    The proposed system abstracts the nature of the DUT. It prescribes a scheduling and control method for carrying out a Shmoo test by tracking a list of DUTs, heuristic search component, streaming control logic that traverses this queue of chips in round robin fashion, maintains a test state machine that tracks DUT status on the whole system and finally records the results of characterization. This core idea concentrates on maximum utilization of the idle time of the DUTs and hence salvages all the idle time as useful time across the SUT (System under test). The control method also specifies an optimum scheduling configuration to take into account the number of DUTs(

N

                    ), test time quanta ( Tq ) ( Time taken to complete one pass/fail decision on a DUT at a particular knob setting ) and serial test overhead (Ts). The control method also specifies a heuristic search that derives predictive search windows from statistical data of prior similar runs. This can be considered as a heuristic pseudo-

parallel pipeline...