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Process for Specifying and Reviewing Timing Requirements for Automatic Generation and Verification of Timing Data

IP.com Disclosure Number: IPCOM000202452D
Publication Date: 2010-Dec-15
Document File: 4 page(s) / 100K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a software application and business process for the efficient and correct generation of the timing rules of a library cell. The method utilizes pattern matching to allow the software program to describe a large family of functionally equivalent library cells and apply the same template of timing arcs and checks.

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Process for Specifying and Reviewing Timing Requirements for Automatic Generation and Verification of Timing Data

Described is a software application and business process for the efficient and correct generation of the timing rules of a library cell. The method is advantageous over existing processes utilized for library characterization in that, by means of pattern matching, the software program describes a large family of functionally equivalent library cells (e.g., a two-input exclusive-OR (XOR) gate) and applies the same template of timing arcs and checks. This is very useful in library verification, especially when working with 3rd party Internet Protocol (IP) providers, when an automated method of verifying requirements is required. By only specifying a single template that represents an entire family of library cells, the method minimizes the quantification of specification (template) data that must be developed and maintained for the library.

Although timing models can be represented in a variety of formats, such as Delay Calculation Language (DCL), New Delay Rules (NDR), Liberty*, Effective Current Source Models (ECSM), etc., and the documentation that is generated can be represented in a variety of formats, such as Hypertext Markup Language (HTML), Extensible Markup Language (XML), etc., the underlying function across a cell family remains the same. A logic family (e.g., AND2*, NOR3*, MPG*, etc...) is functionally similar but may have differences in physical design. The reasons for that include drive strength differences, technology differences, or different Voltage Threshold (VT) families (RegularVT, HighVT, Ultra HighVT, etc.). The template utilizes regular expression matching to define timing arcs required across all of these cells.

This process provides a method to define a specification for timing model generation by listing the expected timing arcs for a cell family in a template file while utilizing regular expression matching to describe the timing arcs required across all of the cells covered by the template.

Process Flow
1. Start with new library cell
2. Review timing arc requirements based on a datasheet
3. Code timing modes template
• Specify cell family regular expression
• Specify cell-specific regular expression and associate with expected arcs and tests (for each required timing mode)

4. When rules have been developed, read the rules and template into a software program

5. Find subset of loaded library cells that match the 'cell family' regular expression
6. For each timing arc, find all the cells that match the 'cell-specific' regular expression and verify that the timing arc exists

To illustrate a preferred embodiment, Figure 1 represents a segment of a timi...