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Scheme Allowing Asynchronous Program Transfer to Dissimilar Processor Without Notification

IP.com Disclosure Number: IPCOM000202468D
Publication Date: 2010-Dec-16
Document File: 2 page(s) / 32K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method of transferring an executing program from one processor to a dissimilar processor without prior notification of the program is described. The methods incorporates supporting hardware and a set of steps performed by a hypervisor prior to and after the transfer. The apparatus and method can be used when a processor malfunction or other event results in the immediate need to transfer an executing program to another processor when there is insufficient time available to notify the program prior to the transfer.

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Scheme Allowing Asynchronous Program Transfer to Dissimilar Processor Without Notification

Background


It is often necessary to transfer an executing program from one system to another in order to balance workloads, allow maintenance to be performed, or other reasons. In order to support this, either the source and target systems must be identical or appear to be identical, or the program must be interrupted prior to and after the transfer so that it can adjust to the new processor. When the transfer is performed, the hypervisor first notifies the program that transfer is about to occur, and the program must acknowledge that it is ready for the transfer. The hypervisor then transfers the program state to the other processor, enables execution of the program on the processor, and informs the program that transfer to the new processor has occurred. The program then resumes, making any adjustments that may be needed to adjust to the features of the new processor are different from the features the source processor.

In some situations, such as a processor or memory malfunction, the system on which the program is running may unexpectedly encounter a sudden problem that requires the program to be transferred immediately after the current instruction completes. In these situations, there is insufficient time to notify the executing program prior to the transfer, and the program continues to execute after the transfer on the target processor as if no transfer has occurred. Since the program may be in the process of reading or writing registers or using facilities when transfer occurs, all of the resources in use by the program must be identical on both source and destination processors. Any features on the source processor that do not exist on the destination processor must not be used by the program. This requirement to refrain from using features on the source processor that differ from those on the destination processor is a significant restriction since the source processor may contain a large number of very useful features not found on the destination processor. For example, these features may include performance monitoring controls used to optimize performance of the source processor, controls used to tune processor operation, and many other features that enable the source processor to achieve optimal performance.

The method and apparatus described below solves this problem by enabling the program to take advantage of features unique to the source processor while still retaining the capability to be transferred asynchronously to a target processor that does not support the features. The key aspect of this scheme is that it provides the hypervisor with the ability to modify the behavior of features that differ between the source and destination processors temporarily while guaranteeing that the modified behavior does not disrupt program operation. This allows the program to continue to use the features immediately after the transfer...