Addressable Test Structure Host/Client Framework and Methodology
Publication Date: 2011-Jan-26
The IP.com Prior Art Database
Disclosed is an efficient method for compiling content for content masks without excluding any beneficial macros. The solution is an addressable test structure framework where each site is given a pre-determined number of input and outputs. This allows multiple designers to design client macros that fit within a grid location of the host grid, eliminating the requirement for pads.
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Addressable Test Structure Host /Client Framework and Methodology
During development of new semiconductor technologies, special mask sets geared toward characterizing the technology are used. These mask sets are full of a wide range of content (i.e., macros) including test structures, standard cell designs, early customer designs and Static Random Access Memory (SRAM) arrays. The test structure macros include defectivity test structures such as combs and via chains, structures to measure parametrics such as line width and sheet resistance, and structures to measure device performance. Multiple mask sets are used during the development process and are geared toward different goals. For instance, earlier in the development cycle SRAM arrays and customer designs are more modest in size. As bugs are worked out in the process, these designs become more complicated.
Compiling all the content for test mask sets can be very cumbersome because of the many different requirements and different designers preparing content to meet these requirements. Most content is electrically probed for the purpose of evaluation. As a result, a very large proportion of the mask set is used for probe pads. Each design has its own set of probe pads and often the probe pads are much larger than the actual structures being tested. Because of the inefficiency, many beneficial macros are excluded from mask sets due to lack of space. A more efficient method to compile content for content mask sets is needed in order to ensure that all macros are included in the mask sets.
One approach to address this issue is to use smaller probe pads. Probe pad size has shrunk over the years; however, it is difficult to work with sizes under 40nm x 40nm for a standard probe card for a variety of reasons, including the need for automated probe alignment and robust probe pins.
A more efficient use of space is to use an addressable array . Here, a grid of test structures is tested using the same set of pads. Each structure within the grid has an electrical address which, when selected, allows testing of only that structure. Addressable arrays are designed by a single design team; therefore, they are only useful in situations where that design t...