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A novel test structure for simultaneous sensing of local temperature and thermal gradient

IP.com Disclosure Number: IPCOM000203522D
Publication Date: 2011-Jan-27
Document File: 5 page(s) / 166K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention is about a novel test-structure for the simultaneous measurement of the temperature and thermal gradient at any given point in a heterogeneous thermal environment. The test-structure and methodolody to perform such a measurement along with a calibration scheme is described in this publication.

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A novel test structure for simultaneous sensing of local temperature and thermal gradient

Motivation

Thermal problems of dissipating heat from devices are extremely important in many applications ranging from digital circuits, analog circuits to power devices. Unwanted effects such as hot spot formation, thermal runaway, thermal coupling between neighboring devices, etc adversely impact the reliability or the performance of semiconductor devices and circuits. Thus it is essential to work towards the development of better thermal monitoring systems/circuits. Towards this end accurate temperature sensing is of primary importance. Temperature sensing is most commonly done by 1) using diodes (on chip) or 2) by employing the gate of the FET as a resistor to sense the temperature (in cases where the FET is the heat source). 3) A (second) 'sensor' FET is also used in the sub-threshold region wherein the sub-threshold slope correlates directly with temperature. The diode method (1) needs two-point-calibration and cannot be adopted if the backend of line thermal environment is to be sensed. The FET based method (2), is prone to errors arising from variable thermal resistance between the Si-Sio2- interface and method (3) employing the driver-sensor configuration has been found to be unreliable due to less robust reproducibility. Besides, all the above methods are based on temperature measurements at a single spatial point. No thermal gradient information can be gleaned from such sensing. Hence there is a need for a more robust method/sensors that can be used anywhere on the chip BEOL/FEOL as well as provide the gradient information.

Main idea

We propose to sense the local thermal environment of a chip using a simple analog circuit. The circuit described herein (Figure 1) is based on sensing the variable resistance of resistors in a potential divider network. The potential (and any change accompanying it as a result of local heating of the resistors) is fed to the gate of a FET. Subsequently the thermal fluctuations can be read off from the drain current. The advantage of this method is the thermal gradient information can be obtained along with the temperature measurements.

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Figure1. Two identical resistors placed nearby, slightly displaced (spatially) in a potential divider configuration. The potential from the mid-point is fed to the gate of an isolated FET. Above left: Cross-section. Above right: Top View.

A schematic of the proposed circuit is shown below in Figure 2. Assuming the two identical resistors see uneven thermal flux when placed in a thermal environment the resultant change in resistance will cause a shift in the potential between the two resistors. This shift in the gate bias will cause an amplified change in the drain current of the FET. Thus the thermal signatures can be easily captured by measu...