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Semiconductor Device Structure and Method of Manufacture Thereof

IP.com Disclosure Number: IPCOM000203538D
Publication Date: 2011-Jan-27
Document File: 2 page(s) / 26K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to utilize a p-type channel field effect transistor PFET with silicon (or SiGe with reduced Ge) deep Source Drains (not SiGe) in conjunction with SiGe channel to reduce GIDL in the deep S/D perimeter in order to reduce gate induced dratin leakage.

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Semiconductor Device Structure and Method of Manufacture Thereof

Planar bulk device technology is still a desired option for low power space. With high-K metal gate technology, it becomes necessary to use a Silicon Germaniuim (SiGe) channel for p-type channel field effect transistor (PFET) to set the Vt for higher performance devices on the chip. However, owing to the smaller band-gap of SiGe compared to Si, gate induced drain leakage (GIDL) can become significantly larger. This is a bigger problem for higher Vt devices with low channel leakage as they have high channel doping which results in higher GIDL.

One way to mitigate this problem is to use a quarter gap work function metal and reduce channel doping which also results in some loss of short channel control. What is needed is the ability to reduce GIDL for PFETs.

The disclosed invention uses a PFET with silicon (or SiGe with reduced Ge) deep Source Drains (not SiGe) in conjunction with SiGe channel to reduce GIDL in the deep S/D perimeter. Further, the extension may also be replaced by Si to reduce the GIDL in the extension perimeter. Also, the higher band gap of Si results in lower GIDL with some added series resistance in the drain due to valence band offset between the channel and drain creating a small barrier. However, as drain is biased, the impact of barrier is reduced.

In the process of a preferred embodiment: follow the same process sequence as the conventional HiK/metal gate CMOS flow with SiGe c...