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Low-Cost On-Chip Passive Devices Formed By Through Silicon Vias

IP.com Disclosure Number: IPCOM000203775D
Publication Date: 2011-Feb-01
Document File: 2 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

Low-Cost On-Chip Passive Devices Formed By Through Silicon Vias R. Joshi, F. Liu, K. Cheng & L. Hsu The present invention generally relates to the electrical and electronic arts and, more particularly, to method and structure of passive devices formed by through-silicon-vias in a 3D chip stack assembly. Passive devices such as capacitors and resistors have found a wide range of applications in integrated circuit chips. For example, a high-density capacitor is critical in areas-sensitive chip to decoupling and stabilizing signal and power supply lines. As the number of integrated devices and circuits are continuously to increase from generation to generation, less and less chip area is left that can be used for building passive devices. Without sufficient decoupling capacitor, cross-talk noise due to coupling effect of adjacent wires has jeopardized signal integrity in high-speed circuits. Besides, a large capacitor is always needed for many other usages, for example, in PLL (phase lock loop), charge pump, analog circuits and ESD (electro-static discharge) devices. Principles of the present invention is to provide a technique for forming capacitor, resistor and capacitor-resistor network using through-silicon-via (TSV) from a 3D chip stack assembly. An exemplary embodiment of a method for manufacturing such capacitor and resistor network is demonstrated. According to one aspect of the invention, the step-by-step fabricating method of providing TSV as well as TSV-like capacitors and resistors in each thinned chip is shown. Finally, the interconnect of TSVs and TSV-like capacitors and resistors are done by stacking and bonding a plurality of chips on top of each other during assembly period. The invention is described in Figures 1 and 2. The idea is to form passive elements. Referring to Fig. 1, last metal including metal pad 1301 and metal interconnect for capacitor 1302 are formed through the conventional processing. The metal interconnect for capacitor will connect top plate 1201 of the capacitor to power supply 16. Then the wafer or chip is flipped as shown in Fig. 2 which forms the final invention. Referring to Fig 2, the chip is flipped and ready for back-side processing. The back-side process comprises first step of removal the bottom film and second step of polishing to remove the insulating material and partial of bottom electrode as shown in the figure. If dep-etch is used to form the bottom plate, a further thinning is possible. As shown in Fig, both TSV and TSV-like capacitors are formed on a backside thinned wafer. Other structures are possible using such process and methodology.

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Low-Cost On-Chip Passive Devices Formed By Through Silicon Vias

Low-Cost On-Chip Passive Devices Formed By Through Silicon Vias
R. Joshi, F. Liu, K. Cheng & L. Hsu

The present invention generally relates to the electrical and electronic arts and, more particularly, to method and structure of passive devices formed by through-silicon-vias in a 3D chip stack assembly.

Passive devices such as capacitors and resistors have found a wide range of applications in integrated circuit chips. For example, a high-density capacitor is critical in areas-sensitive chip to decoupling and stabilizing signal and power supply lines. As the number of integrated devices and circuits are continuously to increase from generation to generation, less and less chip area is left that can be used for building passive devices. Without sufficient decoupling capacitor, cross-talk noise due to coupling effect of adjacent wires has jeopardized signal integrity in high-speed circuits. Besides, a large capacitor is always needed for many other usages, for example, in PLL (

phase lock loop), charge pump, analog circuits and ESD (electro-static

discharge) devices.

Principles of the present invention is to provide a technique for forming capacitor, resistor and capacitor-resistor network using through-silicon-via (TSV) from a 3D chip stack assembly. An exemplary embodiment of a method for manufacturing such capacitor and resistor network is demonstrated. According to one aspect of the invention, the...