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treatment of resistive loads in current mirror circuits by substitution of fet loads

IP.com Disclosure Number: IPCOM000204576D
Publication Date: 2011-Mar-04
Document File: 1 page(s) / 25K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a system to automatically generate logic states for differential logic with resistive pull-ups for the purpose of timing analysis.

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treatment of resistive loads in current mirror circuits by substitution of fet loads

A method is needed to generate logic states for current steering logic with resistive loads. Logic state analysis on complimentary metal-oxide semiconductor (CMOS) circuits accepts circuits constructed entirely from nMOS and pMOS devices. In the default logic state analysis process, resistors are treated as logical shorts, which would connect the current steering circuits' outputs to power supply (VDD) rail values, and no useful logic states would be generated.

The inclusion of current-mode logic (CML) gates introduces passive resistors into the circuit. Existing practice for current-mode logic is to describe input-output state relationships manually by customized templates. With passive resistors substituted by properly biased MOS, the CML can be processed by state analysis, where the effects of the resistors are accounted for. No known prior art closely matches the disclosed invention.

The disclosed solution is for active load substitution. The key idea of this invention is to substitute the resistive loads on complementary legs of a current steering logic circuit by cross-coupled positive-channel field-effect transistors (PFETs). This results in state analysis correctly deducing the logically correct states for both legs of the circuit.

The active load substitution approach includes the following components and stages:
1. pFETs replacing pull-up resistors in CML
2. Gate pins o...