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On-die PLL phase jitter measurement circuit

IP.com Disclosure Number: IPCOM000204782D
Publication Date: 2011-Mar-10
Document File: 2 page(s) / 148K

Publishing Venue

The IP.com Prior Art Database

Abstract

The disclosure describes an On-die PLL phase jitter measurement circuit

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Patent Disclosure  :           On-die PLL phase jitter measurement circuit

Date                           :           21-Jan-2010

Background and problem statement

Current clock phase jitter measurements require large and expensive 3rd-party equipment to evaluate clock quality. Such experimental setups are therefore uncommon and inconvenient for thoroughly evaluating high-volume devices across configuration spaces.

Solution Summary

Each of PLLs has an integrated phase-frequency detector (PFD) for measuring the analog difference between the VCO-generated clock and the externally generated reference clock. The up/down outputs from the PFD typically feeds the VCO, but can also feed a digital-to-analog (D2A) converter. This D2A can be clocked on the reference clock, and the phase quality of the generated clock can then be inferred by the cycle-to-cycle variation of the D2A output.

Invention Description

Below is an example diagram of what the proposed integration of the jitter meter inside a PLL system could be.

The diagram is as would be expected; the PFD’s up/down outputs are routed to a D2A, whose digital output bits are registered and then routed to an analysis circuit.

In this type of setup, the D2A could watch either the UP signal, or the DOWN signal, or some combination of both. As an example, assume the D2A is converting the UP signal. Below is an example signal diagram of what the D2A would see, with the sample edges overlaid based on the reference clock timing.

As for the analysis of the register outputs, that is dependent on the application. If in this example the D2A was 8 bits wide, it would imply a set of 256 steps between Vmin (0V), and Vmax (say, 0.25V). This would put each step at just under 1mV.

If the application logic watching this output were to read the following set of values, then the logic could conclude that this was either above or below the desired threshold, and perform other tasks as necessary.

Cycle #

D2A Value

1

192

2

194

3

194

4

191

5

190

6

193

7

191

8

196

9

192

As an example, a running average would provide a baseline value that could be compared to the instantaneous value. For the sample values given above, the average D2A value is ~192.5. Application logic could evaluate the av...