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Method and System for Manipulating S/390 General Registers and Millicode General Registers in Both ESA/390 and z/Architecture Architectural Modes

IP.com Disclosure Number: IPCOM000206054D
Publication Date: 2011-Apr-13
Document File: 3 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for manipulating S/390* General Registers and Millicode General Registers in ESA/390* and z/Architecture* Architectural Modes is disclosed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

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Method and System for Manipulating S /390 General Registers and Millicode General

Registers in Both ESA/390 and z/Architecture Architectural Modes

Disclosed is a method and system for manipulating S/390 General Registers and Millicode General Registers in ESA/390 and z/Architecture architectural modes.

In ESA/390 Architecture Mode, the General Registers provided by the architecture are 32-bits in length. With the development of the z/Architecture Mode, the architected General Registers were increased to 64-bits in length. To support both ESA/390 and z/Architecture architectural modes, the internal hardware of the current design implements 64-bit General Registers for the operating system, as well as a separate set of 64-bit General Registers for use by the internal Millicode for execution of Millicode routines.

In z/Architecture, a program can run in either the existing 24/31-bit addressing mode, or it can run in the 64-bit addressing mode. While running in either ESA/390 Architecture Mode or in z/Architecture Mode with 24/31-bit addressing mode and executing most instructions that are valid in ESA/390 Mode, only bits 32-63 of the 64-bit General Register are modified. When executing these same instructions in z/Architecture Mode with 64-bit addressing mode, all of bits 0-63 are modified. In addition, some instructions require only bits 32-63 of an architected General Register to be modified, with bits 0-31 untouched, even in 64-bit addressing mode.

For architected instructions that are implemented in Millicode it is often the case that the architected General Registers used by the operating system must be copied into Millicode General Registers for execution. The final results are then written back into the architected registers. With the different addressing modes placing different requirements on the number of bits that would need to be inspected and modified by the many Millicode routines, it is a performance inhibitor to check all of the addressing modes prior to manipulating any of the General Register information.

The method and system disclosed herein provides a means to transfer the correct bits

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to the Millicode General Registers for proper Millicode execution, and then subsequently to transfer the correct bits into the architected General Registers, and leave bits 0-31 unmodified when appropriate.

During Millicode execution there are a number of controls that take effect to enhance Millicode execution. Most of these are in registers called Millicode Control Registers (MCRs). The method and system disclosed herein involves setting bit 2 of the register MCR41 to the current addressing mode of the operating system at each entry into a Millicode routine for instruction execution. It is set to '0'b if the operating system is in 24/31 bit addressing mode, and set to '1'b if in 64-bit addressing mode.

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