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Method to improve homogeneous multi-core chip efficiency by altering core mapping based on core performance data

IP.com Disclosure Number: IPCOM000206439D
Publication Date: 2011-Apr-26
Document File: 2 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to improve efficiency of a multi-core, multiprocessor system. Cores are ranked according to efficiency measurements and data is stored on the chip. Cores are assigned work by the kernel according the stored rankings such that the most efficient cores are assigned work first.

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Disclosed is a method to improve efficiency of a multi-core, multiprocessor system. Cores are ranked according to efficiency measurements and data is stored on the chip. Cores are assigned work by the kernel according the stored rankings such that the most efficient cores are assigned work first. A typical embodiment of this method would be used on the chips of a High Performance Computing (HPC) system that has a large number of multi-core processors.

    Power usage and cooling requirements are becoming big factors in the design and implementation of computer systems. Larger systems typically have hundreds or even thousands of processors in use, with most processors having multiple cores.

Not all applications take

advantage of every core on a processor 100% of the time. For example, a single threaded Message Passing Interface (MPI) program may only use one core on each node of a multi-core system. There can be differences in the power efficiency of different cores within a single, homogeneous, multi-core processor. If systems took advantage of this fact, then applications could have processes/threads mapped such that as much work as possible is performed on the most efficient cores on each node. The power savings are amplified when spread out across several thousand nodes on larger HPC systems.

    The main idea of the invention requires that each core is ranked against the other cores on the same chip according to an efficiency measurement. The efficiency could be measured based on several related factors including, but not limited to, voltage, operating temperature, or mean time between failure. These rankings can then be used to alter a logical mapping of the cores on the processor so that the most efficient cores are used most often. This will result in increased efficiency for the entire processor.

    The core rankings could be adjusted over time because of changes in the system. For example, if the connection between a core and its heatsink is becoming less effective, it may begin to produce more heat during operation, lowering its ranking. Logically remapping the cores would help maintain system performance without producing excessive heat. Using less power on an HPC system has several advantages: Costs less to operate

Produces less heat and requires less cooling

Extends the life of system components

    Alternative ranking profiles could also be loaded onto a chip to induce a different desired behavior. For example, profiles could be loaded for maximum power efficiency, maximum speed, etc.

    The first step is to profile each core on a node according to how efficient i...