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Moving Software In-line Feature, via EXecute, into Hardware Fetching for Code Packing and Functional Line Touching

IP.com Disclosure Number: IPCOM000206775D
Publication Date: 2011-May-06
Document File: 3 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and system for moving software in-line features into hardware fetching for code packing and functional line touching.

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This is the abbreviated version, containing approximately 40% of the total text.

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Moving Software In-line Feature, via EXecute, into Hardware Fetching for Code Packing and Functional Line Touching

There are multiple ways to implement complex instructions. The Reduced Instruction Set Compute (RISC) processor simply strings multiple instructions together in the compiler and then performs execution on these. With use of software, this group of instructions may be performed as a function or method. In such a manner if the function is in-lined when the compiler compiles the code, it essentially removes the function call and places the function code into all places within the code from where the function is called. The trade-off implied here is that for a larger storage image, less branches must be handled. Less branches decreases direction change; however, a larger storage image implies additional resources requirements at the rate of in-line use. A Complex Instruction Set Computer (CISC) processor has gone a step further to create complex hardware instructions which do not require a string of simpler functions to perform an identical operation. Doing so has eliminated creation of simple instruction streams in certain instances, but there is still next level of complexity, short string of complex functions, that even the CISC processor can not currently handle from a hardware state.

To implement certain complex system functions, CISC machines have millicode routines which go off and perform a number of operations for one specified hardware instruction. For such instances, there are entry and exit branches which hurt performance. However, this negative value is offset by positive gains. For some of the system functions, it is necessary that there be no unrelated (or unnecessary) cache activity while a function is executing, such as loading lines into the L1 cache for translating addresses. For example, when updates to time-of-day clock are taking place, they must occur within a certain amount of time and therefore cannot tolerate long delays. For prior processors having a single cache, use of operand fetches was applied. These problems have been dealt with by making sure that all lines that might be referenced during the function were, at one point, in the L1 cache before the function began. This was assured by making an operand line-touch reference to the lines just before the function began. This caused any lines that were not already in the cache to be loaded, such that during execution, the data would be in the cache. This was performed using an ordinary instruction that caused a fetch from the storage locations of the given line. Unfortunately, for processors applying the above techniques, this only works to make sure the data is in the operand cache. Therefore, when going to a split cache, it is also required to have a method to obtain lines into the instruction cache. Prior techniques demonstrate that by performing a Branch on Conditional Relative (BCR) instruction with a mask of zero, causes a line touch as...