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Method and Apparatus for performing timing improvement on nets cross blockage

IP.com Disclosure Number: IPCOM000206923D
Publication Date: 2011-May-13

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention provides a method and apparatus for timing improvement in a placed and routed design of a VLSI chip containing blockages. The present method seeks all the nets with timing violations and identified the ones cross blockages in a placed and routed design of a chip, and categorizes them into different groups according to blockages, so that each group can be processed separately to yield higher quality solution; The present method performs timing prioritized violation correction on blocked nets for reasonable physical resource distribution; The present method performs timing improvement with timing slack, placement and congestion awareness, to fix timing violations and also minimize placement and routing disruptions.

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Method and Apparatus for performing timing improvement on nets cross blockage

At present, it is very commonplace for an integrated circuit designer to perform manual timing improvement on nets cross blockages especially when the blockage has big size, like insert buffers in the failing path to repower a net to fix electrical violation etc. Buffer insertion with blockage awareness is well recognized as an important technique in VLSI chip implementation. In patent No

No.

. 6615401,

a method of "BLOCKED NET BUFFER INSERTION"is provided, a blocked net can be identified with this method, and a desired connection path

between a pair of points of a net separated by one or more blockages can be determined. In patent No

No.

. 6898774, a method of "Buffer

Insertion with Adaptive Blockage Avoidance"is provided, which inserts buffers into integrated circuit routing trees and dynamically modifies a Steiner tree configuration as needed to derive a maximal slack solution that takes into account blockages. In patent No

No.

.

7137081, a method of density biased buffer insertion is provided given the tiled Steiner tree topology map and the density values of the tiles, it obtains an asymmetrically distributed set of candidate buffer insertion points between a source and a sink. Therefore, with above methods, the conventional process can be described as: during timing optimization, an integrated circuit designer examines the timing reports and attempts to fix violations, for cross blockage nets, the designer needs to identifythem and perform timing improvement one after another till timing clean .

One problem of above methods is that they mainly focus on physical implementation and there is no timing information considered, therefore the timing violations may not get fully solved or may even make timing degrade after processing .

Another problem of above methods is that all the nets are identified and processed individually so there is no comprehensive consideration of timing priority and physical resource distribution, also a net is identified as cross blockage only when any point of the net exist in blockage occupied area which misses the ones very nearby the blockages but no point inside of them .

To meet timing requirement is one of the most significant jobs of design implementation, therefore a method to efficiently improve timing on cross blockage nets is required .

This invention provides a method and apparatus for timing improvement in a placed and routed design of a VLSI chip containing blockages . The present method seeks all the nets with timing violations and identified the ones cross blockagesin a placed and routed design of a chip, and categorizes them into different groups according to blockages , so that each group can be processed separately to yield higher quality solution;

The present method performs timing prioritized violation correction on blocked nets for reasonable physical resource distribution ;

The present method performs...