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A method of timing estimation using trunk pre-wiring in ASIC design

IP.com Disclosure Number: IPCOM000206926D
Publication Date: 2011-May-13

Publishing Venue

The IP.com Prior Art Database

Abstract

Nowadays, the HSIF(high speed interface) is more and more critical in ASIC design closure, there will be more resource and time cost in early satge. This invention introduced a new methodology to do the prewire of HSIF quickly in early stage, and it could be reused in later phase, in order to reduce the design risk and TAT(turn around time)

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A method of timing estimation using trunk pre-wiring in ASIC design

Nowadays,

          in ultra deep sub-micron ASIC technology, especially for 65nm and beyond, the HSIF(high speed interface) is more and more critical in design closure, on the other hand, due to technology and integration moving forward, the timing mismatch between pre-wiring stage and post-wiring stage is more and more significant in the design process, which add much difficulties to timing closure

   HSIF is critical in timing closure, it's required to be analyzed in the design early stage, to minimize design churn in later phase, on the other hand HSIF usually has little margin, it requires accuracy, it needs placed, clocked and pre-wired(wired nets before full-wiring) HSIF circuits to analysis timing. In the design early stage, the nets are usually not wired yet, it uses stainer estimation to evaluate timing, it results in timing mismatch when the nets are wired, will add more TAT(turn around time) in timing closure

   The net electrical parameters lie on the wire length, layers and wire width, before the detail routing, the nets parasitic and delay uses stainer estimation, while after detail routing, the nets parasitic and delay uses real wires, but the real wires may various in wirecode, layers and shape to stainer estimation. While the net resistance(R) and capacitance(C) is highly depend on the wirecode, layers and shape of the net,

The net delay is highly depend on R x C

   
The driving gate delay is highly depend on C
From the analysis above, we can find the nets parasitic and delay various between pre-wiring stage and post-wiring stage, results in timing mismatch. For those HSIF wires, this mismatch would cause more iterations in timing closure, results in longer TAT, especially when the design frequency is high

Current design methodology requires extra resource and effort paid, to ensure the HSIF circuits need to go through all the process in design early stage, these process are:
1. floorplan, all the macros and IOs need to be placed on the chip, ports need to be assigned, and physical cells like decaps and ESDs need to be inserted, for HSIF related, the IO cells and IO decaps, some interface hard macros, as well as clock macros like PLLs and deskewers need to be placed and aligned
2. placement, it including pre-placement and full-placement, for HSIF, the IO affinity and timing critical latches need to be preplaced(placed circuits before full-placement), and all other cells are placed during full-placement
3. clock opt, clock nets need to be repowered, for HSIF clocks, usually a special buffer as SCB(structural clock buffer) is used as clock drivers, it has stronger driving strength and larger size, so it needs carefully inserted and placed
4. pre-wiring, once it's clock opted, the clock nets need to be pre-wired to get the accurate net parasitic, for data path, some of the critical net also need to be pre-wired, for HSIF, the pre-wires usually use high layers and wide wir...