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CHINA - An Apparatus of A Novel Sense Amplifier Self-Margin Detection Logic to Reduce SRAM Dynamic Power

IP.com Disclosure Number: IPCOM000206932D
Publication Date: 2011-May-13
Document File: 8 page(s) / 109K

Publishing Venue

The IP.com Prior Art Database

Abstract

The disclosure provides an apparatus to reduce active power consumption of sense amplifier during read operation in CMOS SRAM memory. The apparatus is made up of a voltage margin detector, a comparator and a trimmable reference generator. The voltage margin between dummy true and complementary data lines are detected, and compared with the fixed reference voltage generated by voltage generator. Once the detected margin is greater than reference voltage level, sense amplifiers are disabled. The reference voltage is trimmed based on sensitivity of SRAM sense amplifier and process skew, so that the active time of sense amplifier is reduced and self-adaptive with the process, voltage and temperature condition of SRAM memory. Thus, the active power of sense amplifier is reduced by reducing the active time.

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CHINA - An Apparatus of A Novel Sense Amplifier Self-Margin Detection Logic to Reduce SRAM Dynamic Power

In a CMOS static random access memory (SRAM) read operation, voltage margin between true and complementary bit lines starts to build up based on the present state of the selected SRAM cell. The voltage margin propagates to sense amplifier through true and complementary bit lines. This voltage margin is generally tens mili-volts to hundred mili-volts. When sense amplifier enable signal is pulled high, sense amplifier is activated and ampilfies this small voltage margin to a logic 1 or 0 on the output.

Plenty of the power consumes by sense amplifier when it is activated. In an empirical SRAM design, active time of sense amplifier is usually set to be 1.5 times of its resolution time. This over-design costs extra power consumption, and even affects memory access time.

Prior Art [1], "Differential current sense amplifier circuit and sense amplifier circuit for evaluating the memory state of a SRAM semiconductor memory cell", described a method of self-deactivation of SRAM sense amplifier. But it focused on differential current amplifier which is not die size efficient for a SRAM design.

Prior Art [2], "Dynamic sense amplifier for SRAM", introduces a dynamic sense amplifier including a pre-amplifier to amplify small signals and a main sense latch coupled to pre-amplifier. The dynamic sense amplifier is configured to consume small direct current power.

The object of the present disclosure is to provide an apparatus to reduce extra sense amplifier power consumption caused by the over-design.

An apparatus of reducing SRAM sense amplifier active time, and power consumption thereof is provided. The apparatus consist of an extra comparator to self detect the voltage margin between dummy true and complementary data lines, then return a shut-off signal for sense amplifier once the voltage margin is greater than a referenced voltage level . Thus the sense amplifier active time is self-adaptive with the process, voltage and temperature condition of a SRAM memory. By reducing the active time, no more extra power is consumed compared to the empirical design.

As shown in the Fig. 1, Druing the typical read operation in SRAM, voltage margin between true and complementary bit lines starts to build up based on the present state of the selected SRAM cell. The voltage margin between bitlines propagates to true and complementary data lines through bit muxes (bit switches).

The present disclosure introduces a novel self-margin detection logic,

dummy data lines and compares it with a reference voltage (

reference voltage level is depending on the sensitivity of SRAM sense amplifier and process skew. Typically it can be set to 30-100mV depending on different process technolologies for sense amplifier to amplify the voltage margin built on the true an...