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Hierarchical PADCAGES for VLSI DESIGN

IP.com Disclosure Number: IPCOM000207315D
Publication Date: 2011-May-25
Document File: 2 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for early technology feedback during development and manufacturing of Very Large-Scale Integration (VLSI) chip products. The hierarchical approach enables testability while using fewer metal layers.

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Hierarchical PADCAGES for VLSI DESIGN

A Very Large-Scale Integration (VLSI) chip is the key component for an electric system. As the technology is scaled in nano-meter generation, it is important to employ the most advanced technology as early as possible. This requires designing a product while considering the development and manufacturing issues. The key considerations are (1) early technology feedback using fewer metal layers, and (2) a simple method to find the key technology weakness in development and manufacturing.

The principles of the disclosed invention provide a method for early technology feedback during development and manufacturing. The following aspects provide a more effective diagnostics methodology for the development and manufacturing; the product includes:
• The first padcage and the second within the chip design, where the first padcage is used for the product testing using fewer metal layers with limited functionality. The second padcage is used for the product test using fully processed metals with full chip functionality.

• The first padcage and the second within the chip design, where the first padcage is isolated from the second padcage for the first testing point, and is connected to the second padcage for the second testing point.

• Multiples of the padcage within the chip design, where at least one of them is tested using a different manufacturing process.

• Multiples of the padcage within the chip design, where at least one...