Browse Prior Art Database

Co-centric Alignment and Overlay Target

IP.com Disclosure Number: IPCOM000207316D
Publication Date: 2011-May-25
Document File: 5 page(s) / 57K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a co-centric alignment mark and multi-layer overlay target configuration that represents the reference layer and all expose layers that align to the reference layer.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 36% of the total text.

Page 01 of 5

Co-centric Alignment and Overlay Target

This disclosure addresses the current inability to deconvolve expose and reference layer placement error contributions to overlay error that precludes optimum in-line overlay control.

Current generations of integrated circuits (ICs) are comprised of more than 50 layers, structures sequentially patterned on a single substrate. Exposure by a lithography tool is the principal means of creating the patterns in photoresist films that are subsequently processed to create permanent structures on the substrate or wafer. Successful fabrication requires control of the relative position, or overlay (OL), of exposed patterns to prior layers. OL tolerance of less than 10 nanometers (nm) is often required in current IC manufacturing. These tolerances can only be achieved by the independent measurement and control of expose layer and reference layer contributions to the OL error with a precision of 1 nm and below in IC manufacturing.

OL control is currently achieved by two successive pre- and post-exposure process steps: alignment and overlay metrology.

Alignment:


Alignment is the pre-exposure means by which the lithography tool registers a new layer to an imperfect "reference" layer. Alignment marks printed on reference layer, denoted by the subscript R , at design locations, DR , are measured, using optical detection combined with wafer stage metrology, to determine a set of actual locations,

A

R = (

R , is the mark placement difference between the actual mark location

and its design location:

δ

R =

The alignment error, δ

R . The

X

AR

AR

).

locations are (

XDR , YDR ) and

A

X, Y ) coordinates in the wafer plane: DR = (

, Y

"Alignment error", δ

A

R - DR @ DR (1)

R , varies over the wafer due to placement errors introduced during

the reference layer exposure, process-induced wafer deformations between the reference layer and expose layer, and chuck-induced deformations prior to alignment at the expose layer.

Alignment uses an alignment model to interpolate/extrapolate among measured alignment marks and map the alignment error onto lithography tool adjustments that conform the ensuing expose layer, E , to the reference layer. In other words, alignment adjusts the model predicted placement of the patterns about to be exposed, PE , to minimize the residual error, ε

R = PE - AR , at the alignment mark locations and, by

modeling inference, at all other locations on the wafer as well.

Alignment must be performed on every wafer to be exposed on a lithography tool. When there is no existing layer on the wafer, only a coarse alignment can be performed

1


Page 02 of 5

with respect to the substrate perimeter, typically pre-marked by an orientation notch. The first printed layer must contain alignment marks to become the reference layer for subsequent fine alignment at the expose layer. Current practice is to place the alignment marks in the scribe-line of the exposure field. The full wafer is patterned by sequent...