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Utilizing Ring Structure as Temporary Storage Buffer

IP.com Disclosure Number: IPCOM000207318D
Publication Date: 2011-May-25
Document File: 3 page(s) / 26K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to minimize the need to reject Read commands from the Processor without increasing the number of buffers for the return data. The invention offers the alternative approach of sending the data around the ring again so that the ring acts as temporary storage.

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Utilizing Ring Structure as Temporary Storage Buffer

Memory-mapped input/output (MMIO) is a method of performing input/output between the central processing unit (CPU) and peripheral devices or hardware registers in a computer.

One implementation option is for each hardware register to monitor the CPU's address bus and respond to any of the CPU's access of device-assigned address space, connecting the data bus to a desirable device's hardware register. [1]

Another option is to build a ring which contains one MMIO master and several MMIO slaves.

The MMIO master is responsible for accepting Read/Write commands from the Processor bus and delivering them on the register ring. This ring is built from several slaves where each of them is responsible for several registers. When a slave receives the command from the ring, it decodes the command to determine whether the command is for one of its registers. If the command is not for one of its registers, then the slave just returns the command back to the ring and passes it to the next slave without touching it.

If the command is targeted to one of its registers, then the slave either takes the data from the command and writes it to the relevant register (in case of a write command) or reads the relevant register and puts its data on the ring (in case of a read command).

For a read command, when the MMIO master receives the packet back from the ring, it should extract the data and forward it to the requesting processor.

A problem can happen if the MMIO master does not have an available buffer for the incoming data; then, the data will become lost.

In order to prevent that, the master should accept a new Read command from the Processor bus only if it has an available buffer for it. When the MMIO does not have an available buffer for the return data, the MMIO master should reject this command. This would cause the Processor to re-issue this command and increase traffic on the Processor bus.

To reduce the number of rejected Read commands, the system needs an increased number of buffers; however, this costs in more in terms of chip area and power consumption.

The disclosed invention is an effective method for minimizing the need to reject Read commands from the Processor without increasing the number of buffers for the return data.

In a ring (or similar) topology, when a target resource (e.g., device register) is read and the system performs several cycles before the data to returns to the system bus, it could

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happen that the bus is not able to accept the data. Or, if there is a data buffer to temporarily hold the data before being sent to the system bus, the temporary staging buffer could be full when the data comes back from the target resource.

In this case, the disclosed idea offers an alternate solution: rather than increase the size of that staging buffer, the system sends the data around the ring again so that the ring acts as temporary storage. The reason to do this rath...