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Timing Aware Post Mask ECO FLOW for Metal ‘ONLY’ revision

IP.com Disclosure Number: IPCOM000208388D
Publication Date: 2011-Jul-06
Document File: 7 page(s) / 215K

Publishing Venue

The IP.com Prior Art Database

Abstract

As the functionality packed in single silicon is increasing and time to market remains critical, verification continues not only till the end stages of physical implementation, but also leave room for many more bugs to be caught during post silicon validation. Almost all the taped-out designs see the necessity of functional Engineering Change Orders (ECO’s) found during Post Silicon Validation. Due to this, many times we have a new revision of a previous silicon, which prefers metal ONLY eco’s (to save $$$). Spare gates are present to take care of these functional eco’s, but the timing shift due to these fixes sometimes become critical and difficult to be cleaned with the existing placement of spare cells. Our idea is to not compromise on the design capabilities (by decreasing frequency or functionality) and maintain same time to market (avoiding a re-spin from synthesis) by using the existing gates of other data paths (hence, reusing active layer mask) with higher positive slacks. Instead of using spare gates, the gates from paths with good margins are thus used to perform the timing critical functional ECO (and functionality of disturbed paths is inturn maintained by spare gates which are in vicinity).

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Timing Aware Post Mask ECO FLOW for Metal ‘ONLY’ revision

 

ABSTRACT

As the functionality packed in single silicon is increasing and time to market remains critical, verification continues not only till the end stages of physical implementation, but also leave room for many more bugs to be caught during post silicon validation. Almost all the taped-out designs see the necessity of functional Engineering Change Orders (ECO’s) found during Post Silicon Validation. Due to this, many times we have a new revision of a previous silicon, which prefers metal ONLY eco’s (to save $$$). Spare gates are present to take care of these functional eco’s, but the timing shift due to these fixes sometimes become critical and difficult to be cleaned with the existing placement of spare cells. Our idea is to not compromise on the design capabilities (by decreasing frequency or functionality) and maintain same time to market (avoiding a re-spin from synthesis) by using the existing gates of other data paths (hence, reusing active layer mask) with higher positive slacks. Instead of using spare gates, the gates from paths with good margins are thus used to perform the timing critical functional ECO (and functionality of disturbed paths is inturn maintained by spare gates which are in vicinity).

PROBLEM STATEMENT

When we encounter a bug at post silicon validation and functional ECO(s) need to be done to get a new revision of silicon, we try to reduce time to market and save money by minimizing the changes. One of the best ways to achieve these is to limit our ECO’s to metal ONLY. For such ECO’s  spare cells are utilized, but many times due to distance of the spares or usage of multiple spare gates new timing violations in the earlier clean design are introduced. At this stage re-synthesis or re-placement of the design would mean a silicon delay of many months, besides the increased mask cost due to non-reusability of active layer masks.  

PROPOSED ALGORITHM

The basic idea of this algorithm is an extension and enhancement of the work done by Chen et. Al.1 Let the gates along the functional ECO path are treated as a routing tree. Assume

Fig1: The model of ECO path

The extra wire-capacitance (Cwextra) that can be safely driven by the driver cell, gA(i) can be written as

……...…….Eqn I

Cwextra(i) =  Extra Wiring Load that gA(i) can drive

Cmax(i) = maximum Load that gA(i) can drive (from .lib)

Ci(j) = Input gate capacitance of Fanout cell g(j) (from .lib)

Cw(j) = Wiring Capacitance of Fanout Cell g(j) (from layout)

Ci(k) = Input gate Capacitance of added ECO cell (from .lib)

Adding extra load at the output of gA(i) will change its output transition hence delay of fan-out gates g(j) and gA(i+1). Also it is important to note that the total capacitance seen by the driver cell, gA(i) is sum of wiring load (Cw) of its fanout (FO) cells and their input gate capacitance (Ci).

CASE I – Cwextra(i) > 0

We need to select all cells in the bounding polygon of...