Browse Prior Art Database

Programmable Array Local Clock Generator for High Frequency Operations

IP.com Disclosure Number: IPCOM000208533D
Publication Date: 2011-Jul-11
Document File: 4 page(s) / 228K

Publishing Venue

The IP.com Prior Art Database

Abstract

A design is disclosed for a programmable array local clock generator for high frequency operations.

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This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 4

Programmable Array Local Clock Generator for High Frequency Operations

Disclosed is a design of a programmable array local clock generator for high

frequency operations.

Figure 1 illustrates current 32nm pLCB topology.

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Figure 1

The current topology includes custom array programmable delay & pulse width (PW)

control blocks. It also includes feedback (FB) delay insertion (external) for PW

addition.

The topology supports limited maximum cycle time due to long FB delay affecting

PW as illustrated in figure 2. Also, relax dly and PW settings are not workable at fast

cycle time.

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Page 02 of 4

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Figure 2

The design disclosed herein reduces feedback path delay of the existing art pLCB by

eliminating 2 inverter stages in its chop block. Figure 3 illustrates the new 22nm

array pLCB Topology.

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Figure 3

Figure 4 illustrates the cycle time improvement for the new array pLCB.

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Page 03 of 4

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Figure 4

Further, the design includes a new programmable pulse width block with merged

global timing function (dmode, mpw1, mpw2). Figure 5 illustrates the new PW

control block with additional functions.

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Page 04 of 4

Figure 5

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