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Cache Memory Power Reduction Through Valid Bit Detection

IP.com Disclosure Number: IPCOM000209079D
Publication Date: 2011-Jul-26
Document File: 6 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

In SRAM (Static Random Access Memory) and register file memory arrays, an extra bit is sometimes added to a memory location to denote the validity of data stored. This bit is returned like any other bit at the memory location during a read access. If a valid bit denotes invalid data, downstream logic will ingore the data resulting from the read access. If invalid data read is disgarded, a lower power state can be assigned to the remaining bits at the storing of the invalid data. The following article describes the organization, circuitry, and advantages of having such a scheme.

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Cache Memory Power Reduction Through Valid Bit Detection

Disclosed is a novel method to decrease switching and leakage power in memory arrays.

SRAM memory cells use very small device sizes to maximize storage density. With CMOS (Complimentary Metal Oxide Semiconductor) transistors, smaller devices tend to have greater source-drain leakage than bigger devices. For this reason, cell leakage power can be a significant contributor to overall SRAM array power.

With increasing needs for power reduction, SRAM cell leakage is one candidate that can be targeted.

Cache memory arrays sometime use valid bit. Each logical row contains at least one bit to indicate if the entry is valid. This bit is accessed along with any other bit in the entry. The access of an entry occurs regardless of the state of the valid bit. Traditionally, logic downstream from the array discards the data returned from a read
operation if an entry is invalid.

The memory cell used for the valid bit can be different than a traditional 6 transistor cell. One example of that difference is a reset port that can switch cell state without the need for a standard wordline-enabled access.

Figure 1 describes a traditional 6T SRAM cell.

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Figure 1

Figure 2 describes a 6T cell with an reset port driven by the signal 'reset.' This particular SRAM cell can be reset by driving 'reset' high. 'wl' does not need to be activated for this kind of reset operation. This particular cell also has an output port 'out' that continuously drives the value stored in the SRAM cell without the need for 'wl' to be activated.

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Figure 2

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Figure 3

Figure 3 represents a high level diagram of a typical cache memory array. Each column contains a pair of bitlines that are driven to complementary states during read/write and are traditionally precharged to the voltage supply. The true and complement bitlines drive a sense amplifier or full swing logic gate (labeled bitline eval) to convert the complementary signals to a single-ended signal for use downstream.

The read/write access is normally triggered by a wordline driver. The wordline driver fires after an address has been received from external logic and decoded. The node labeled 'wl' in Figure 1 and in Figure 2 enables an SRAM memory cell for read/write by turning on the cell's passgate devices.

Header and footer devices are widely used to reduce leakage in CMOS circuits. The concept involves adding a device in series with the power supply or ground. Since leakage across an "off" device increases exponential with source-drain voltage, a header/footer device can reduce leakage current significantly by eliminating any "off"

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devices with a full ground-power supply potential across the source-drain. The concept of header and footer devices are shown in Figure 4 an...