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A NOVEL METHOD OF OUTPUT CLOCK SEARCH ON ATE FOR TEST TIME REDUCTION

IP.com Disclosure Number: IPCOM000209604D
Publication Date: 2011-Aug-10
Document File: 3 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

In today’s SoC testing on ATE test time reduction is of great concern as because “test time” directly impact gross margin of any SoC. Here we are proposing a method of output clock search in source synchronous interface where output clock can be searched in one go on ATE for AC characterization or at spec testing on ATE. Traditionally output clock is being searched by running the pattern on ATE multiple times and hence consumed lots of test time. As in the proposed method, pattern is being run only once therefore test time incurred is expected to be less than traditional approach of output clock searching on ATE.

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A NOVEL METHOD OF OUTPUT CLOCK SEARCH ON ATE FOR TEST TIME REDUCTION

ABSTARCT

In today’s SoC testing on ATE test time reduction is of great concern as because “test time” directly impact gross margin of any SoC. Here we are proposing a method of output clock search in source synchronous interface where output clock can be searched in one go on ATE for AC characterization or at spec testing on ATE. Traditionally output clock is being searched by running the pattern on ATE multiple times and hence consumed lots of test time. As in the proposed method, pattern is being run only once therefore test time incurred is expected to be less than traditional approach of output clock searching on ATE.

BODY

·           Problem Description: Existing method of output clock search on ATE for Source Synchronous Interface

In source synchronous interface output clock comes out of the SoC. As the arrival of output clock edge of source synchronous interface varies across PVT, therefore to measure the AC specs (setup & hold time) of an interface, arrival of clock edge need to be measured on ATE to perform AC spec testing. In the traditional method output clock is being searched by running the pattern multiple with incremental shifting of capture edge on ATE. And the shifting of capture edge on ATE continues until required clock edge is being found on that particular PVT corner. As the same pattern run multiple times therefore test time is more in traditional approach.

For Example:

If the test time to run the pattern once on ATE is 100milliseconds & assume  pattern required 40 run  before finding the output clock edge, then the overall test time required for output clock search would be  40*100milliseconds i.e. 4seconds.

Fig 1.1

Above figure shows the output clock from simulation and delayed version of it on Si (particular PVT) and it shows the incremental shifting of capture edge (strobe) in multip...