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Method for Tuning the Processing Power Dedicated to Processor Threads

IP.com Disclosure Number: IPCOM000210417D
Publication Date: 2011-Sep-02
Document File: 2 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

A control mechanism that enables the relative priorities of threads on a multi-threaded processor to be adjusted with respect to each other is disclosed.

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Method for Tuning the Processing Power Dedicated to Processor Threads

Disclosed is a processor register, referred to as the "Relative Priority Register" (RPR), that allows a control program to adjust the relative priorities provided by each priority level a "Thread Priority Register" (TPR) on a multi-threaded processor. Using the RPR, a control program is able to tune the relative priorities provided by each priority level of the TPR in order to achieve optimal performance when a given set of programs are executing on the processor threads.

In a processor with 3 privilege states consisting of a hypervisor state (highest privilege), system state (middle privilege for operating systems), and problem state (lowest privilege for applications), the RPR is configurable only in hypervisor state, and the PPR is controlled either in hypervisor or system state. This allows the hypervisor control the relative priority corresponding to each priority level, but at the same time allows the operating system to select the priority level of each thread based on the importance of the task executing on the thread. Existing methods that not provide a RPR require the relative priorities corresponding to each priority level of the TPR to be fixed, making it impossible to increase performance by adjusting the relative priorities of each priority level.

The simplest implementation of this concept is to provide a single RPR. This RPR is subdivided into the same number of fields as there are priority levels. For example, if there are 7 priority levels, the RPR is divided into 7 fields, where each field corresponds to a given priority level.

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Each field, RPn, specifies the relative priority of the TPR priority value n. Placing a 0 in RPn specifies that TPR priority level n is the lowest priority; placing FF in RPn specifies that TPR priority level n is the highest priority. The hypervisor typically ensures that the relative priority for each higher TPR priority level increases (i.e. RP1<RP2<...RP7), although this is not absolutely required. Using this register, the hypervisor can set the relative prio...