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Method and system for Creating Sub-litho Hole in Memory Array with Double Patterning

IP.com Disclosure Number: IPCOM000211199D
Publication Date: 2011-Sep-27
Document File: 4 page(s) / 118K

Publishing Venue

The IP.com Prior Art Database

Abstract

A dual-mask spacer method for creating sub-litho hole in memory array with double patterning is disclosed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 74% of the total text.

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Method and system for Creating Sub -litho Hole in Memory Array with Double Patterning

Disclosed is a method and system for creating sub-litho hole either for forming contact to upper level metals or for forming critical dimension for memory elements. The method involves using two different materials and two masks to define the hole. The two masks are applied as check-board patterns. Spacer technique is used to shrink the size of the hole after exposure. Thereafter, Optical Proximity Correction (OPC) is applied to ensure the open area is round and is barely connected after exposure. Fig. 1 illustrates the first check-board mask open after exposure.

Figure 1

Fig. 2 illustrates a cross-section of the process steps to create the first check-board hole on HM.

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Figure 2

Fig. 3 illustrates the top view of process steps to create the first check-board hole on HM.

Figure 3

Here, material A is the surrounding area where a hole is defined and material B is

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deposited and used as hard mask and spacer. The first check-board pattern is applied for creating the first check-board pattern hole. Thereafter, the same material B is deposited and used as spacer to shrink the size of the hole. Subsequently, a second check-board pattern is applied for creating the second check-board pattern hole. Fig. 4 illustrates check-board second CA mask open after exposure.

Figure 4

Fig. 5 and Fig. 6 illustrate a cross-sectional view and a top view respectively of the...