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Establishing Deterministic Behavior of Processor Sub-System for Pulses on Level Sensitive Interrupt Lines

IP.com Disclosure Number: IPCOM000211222D
Publication Date: 2011-Sep-28
Document File: 7 page(s) / 433K

Publishing Venue

The IP.com Prior Art Database

Abstract

Generic interrupt controllers are usually re-configurable (either by software or hardware) to handle interrupts in various contexts and priorities. For a level interrupt based core, interrupt controllers usually have additional capability for handling pulses from the sources, but they miss the fact that re-configuration can cause a race between the existing/incoming interrupts and the context change, which can create windows in which a level interrupt can be converted to a pulse (glitch) of different lengths. If such interrupt controllers are connected to a CPU that expects only level interrupts, then if there is a pulse or glitch on interrupt lines, the CPU may exhibit non-deterministic behavior including corruption of the previous context’s states. In this paper we propose the addition of a simple logic circuit between the interrupt controller and the processor interrupt handling logic to prevent the CPU interrupt handling logic from sampling pulses, which in turn prevents the CPU from exhibiting non-deterministic behavior.

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ABSTRACT

Generic interrupt controllers are usually re-configurable (either by software or hardware) to handle interrupts in various contexts and priorities.  For a level interrupt based core, interrupt controllers usually have additional capability for handling pulses from the sources, but they miss the fact that re-configuration can cause a race between the existing/incoming interrupts and the context change, which can create windows in which a level interrupt can be converted to a pulse (glitch) of different lengths.  If such interrupt controllers are connected to a CPU that expects only level interrupts, then if there is a pulse or glitch on interrupt lines, the CPU may exhibit non-deterministic behavior including corruption of the previous context’s states.  In this paper we propose the addition of a simple logic circuit between the interrupt controller and the processor interrupt handling logic to prevent the CPU interrupt handling logic from sampling pulses, which in turn prevents the CPU from exhibiting non-deterministic behavior.

BACKGROUND

Systems under consideration have various kinds of interrupts including level-sensitive interrupts.  Existing systems consider the following requirements based on the intended applications, system peripherals, performance and possible context switches based on OS context ID, power management modes, and other system defined modes:

•       For a system having different IPs generating different kinds of interrupts (like level or pulse), interrupt controller needs to handle both pulse and level based interrupts;

•       For a specific application/process, interrupts from certain devices (like Ethernet/USB) may need to be considered as a higher priority than from other devices (like timer).  So interrupts need to be reconfigured (prioritize - de-prioritize or enable - disable) based on dynamic requirements of applications and contexts;

•       For a multi-core system, the same interrupts may be routed to different processors based on the state and availability of the system processors. Such requirements often require masking or unmasking interrupts to certain processors based their availability.

Generally such requirements are handled through software, hardware, or a combination of the two. In 1992-93, interrupt controllers were devised, which were either pre-programmed or dynamically programmed to configure interrupt input request lines as level or edge sensitive [1] and [2].  More recently, in 2010, one company devised a controller that could handle both pulse and level interrupts on the same interrupt line without any configuration by hardware or software [3].  In the same year, another company implemented an interrupt controller (IC) that automatically changed the priority/masking of an interrupt based on the system context.  Whenever there is a context switch, the IC automatically re-configures itself according to pre-programmed requirements for the given context [4].  For a multi-core system, one implem...