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Pulsed Local Clock Buffer with independent back edge shaping

IP.com Disclosure Number: IPCOM000211371D
Publication Date: 2011-Sep-29
Document File: 6 page(s) / 153K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a pulsed local clock buffer (LCB) with independent back edge shaping.

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In chip architecture and design, there are a variety of different latch and clock generation structures used. Currently, the most common configuration used for clock generation and latching is a local clock buffer (LCB) that creates a dclk and lclk which then feeds an L1/L2 pair. One variation of this basic structure is a pulsed design where the LCB creates a narrow lclk which feeds just the L2 portion of a latch or nand gate while the dclk remains high.

    Where pulsed designs can be problematic is in the case of static random access memory (SRAM) designs that use a domino approach for reading and writing the cell. In this case, the narrow or pulsed lclk is used to generate the wordline signal that accesses the cell. Unfortunately, due to the size of the devices within the cell and the amount of time it takes to completely discharge the bitline, the pulsed lclk is typically not wide enough for a read to occur. What many SRAM designs have done to accommodate this is to create a special LCB that includes a feedback path to widen the lclk. This LCB is a one off of the standard LCB blocks used by custom logic and random logic macros (RLMs). These LCBs have very low set-up and hold times for the clock control signals compared to the pulse generator circuits used by ASIC groups which typically have very large set-up and hold times on the clock control signals. While this pulsed LCB is very advantageous, it is limited by the fact that you cannot add in too much delay because, at faster frequencies, the falling edge of the chip clock would eventually terminate the pulse.

    One solution for fixing this problem is a new version of the pulsed LCB used by SRAM designers in 32nm technology that maintains the low set-up and hold times of the clock control signals but is independent of the chip clock. The core idea behind the new LCB is the fast and slow path approach that is often used in basic shaper circuits. Shaper circuits, in general, often consist of a nand gate where the base input is the same for the two legs but there is delay added between the input and one leg of the nand. What this does, circuit wise, is allow the rising edge of the signal to pass through with no additional delay but pushes the falling edge further out in time creating a wider pulse. This can conceptually be applied to the pulsed LCB by changing the base clock generation such that it implements a nand of the chip clock and the delayed feedback path. Thus, the rising edge of the lclk coming out of the pulsed LCB is generated from the chip clock, but the falling edge will always be determined by the feedback path.

    Figures 1, 2, and 3 below show the standard implementation of the pulsed LCB used by the server group in 32nm. The inverters between the pwo and pwi pins in Figure 1 are used to widen the lclk by a set amount of delay; this...