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Method of meta-stable measurement on-chip and dynamic adjusting of synchronization circuits

IP.com Disclosure Number: IPCOM000211734D
Publication Date: 2011-Oct-14
Document File: 6 page(s) / 135K

Publishing Venue

The IP.com Prior Art Database

Abstract

Asynchronous clock domains on the chip became usual practice for improving power consumption and performance. Synchronizers, built on multiple sampling, are placed to resolve possible meta-stability problem.

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Method of meta-stable measurement on-chip and dynamic adjusting of synchronization circuits.

Abstract

Asynchronous clock domains on the chip became usual practice for improving power consumption and performance. Synchronizers, built on multiple sampling, are placed to resolve possible meta-stability problem

Introduction

Cost of synchronizer on data path is increased latency. Number of samplings is defined by frequency (can be seen from Fig1), process case, temperature (Fig3), voltage (Fig2). Worst case is assumed for definition of synchronizer, that leads to overdesign and performance impact.

It should be noted, that tau of latch depends on process parameters, that are not considered critical for cells delay and thus are not controlled well. For that reason, tau can change significantly from chip to chip.

Fig. 1

Fig. 2

Fig. 3

Proposed solution

The proposal is to measure meta-stability severity from special circuit on the specific chip at specific conditions and dynamically change number of samplings in synchronizers, according to measurements.

Meta-stability is measured from FF output delay.

To reduce measurement time, high probability of meta-stable conditions should be generated. One of the ways to do it is balance data and clock to FF circuit and change phase difference between in random way, but in small range. It can be implemented, for example, by slow smooth changing of supply voltage of one clock buffers around the value, that makes phase difference zero.

Measurement...