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Method of Forming a Stacked Silicon Nanowire Device

IP.com Disclosure Number: IPCOM000211772D
Publication Date: 2011-Oct-17
Document File: 4 page(s) / 143K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is provided to form a stacked silicon nanowire device.

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This is the abbreviated version, containing approximately 88% of the total text.

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Method of Forming a Stacked Silicon Nanowire Device

Disclosed is a method of forming a stacked silicon nanowire device.

The method disclosed herein allows forming stacked silicon nanowire devices with distinct structural features. A Rare Earth Oxide (REO) and silicon super lattice is formed on a silicon wafer to facilitate the stacked silicon nanowire formation. The silicon wafer with multiple layers of REO and silicon channels forming a superlattice is illustrated in Fig. 1. REO can be epitaxially grown on the silicon substrate. Further, nanowire patterning is carried out on the silicon wafer, as illustrated by the top view in Fig. 2.

Figure 1

Figure 2

Thereafter, REO etching is performed on the silicon wafer, as illustrated in Fig. 3. The size and geometry of nanowire is then defined on the silicon wafer using oxidation, as

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shown in Fig. 4.

Figure 3

Figure 4

On completing the dielectric and gate deposition on the silicon wafer, gate patterning and spacer pattering is carried out on the silicon wafer, as illustrated in Fig. 5.

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Figure 5

Source/drain (S/D) patterning and epitaxial patterning is then carried out on the silicon wafer as illustrated in Fig. 6. Once the S/D patterning is complete, silicidation is carried out on the silicon wafer. Fig. 7 and Fig. 8 illustrate a top view and a cross sectional view of a silicon contact on which silicidation is carried out. This completes the stacked silicon nanowire formation.

Figure 6

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