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Method and apparatus for design data integrity management in a system hardware design

IP.com Disclosure Number: IPCOM000212345D
Publication Date: 2011-Nov-07
Document File: 9 page(s) / 100K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed invention presents a novel way of handling design changes inherently within the hardware design flow by means of tracking and capturing any logic that undergoes a change. The invention suggests to leverage any tracking tool, that is already available as part of the design flow to enable the design data handling mechanism. The invention also suggests the tracker must maintain work in process version control, based on the design change integration happened in the latest version, thereby to make sure that another similar design can always leverage the latest tested, verified and validated design.

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Method and apparatus for design data integrity management in a system hardware design

A system hardware typically comprises of multiple printed circuit boards (PCB or board), each board with many integrated circuits, active and passive components in it. There are a set of tools needed to design and develop such boards and these tools are used to create and manage the following:


Design data - Schematic, layout and Gerber files


Constraints - Electrical, routing, placement, tolerances, performance


Libraries - Schematic Symbols, Layout footprints, mechanical 3D models, Signal Integrity models and reuse blocks

Development phase consists of many stages and logic design is one of the important phases which aim in establishing the necessary connectivity among different interfaces of the chipsets and other components. All connectivity details are important to achieve intended operation of the board and hence capturing all design information is a very crucial step. Typically, this is accomplished in computer aided environment (CAD) with the help of schematics editor tool. The schematics editor tool facilitates the symbol creation of parts, placement and wiring among them. Schematics output is generated in the form of net list and then it is used by the layout design tool to facilitate the placement and routing process. During logic design phase, multiple designers can work in the same design and hence ensuring integrity of the "design work in process" is an important & critical task. Many a times, there would be need for multiple designers to work within the same design at the same time in order to meet the below challenges:


Short time to market or product GA (General availability)


Limited time to develop PCBs


Rapid pace of multiple change orders across engineering disciplines

In this context, the changes carried out in the "design work in progress" needs to be conceded by experts from respective multiple disciplines such as Physical design, Mechanical, EMI/EMC and Regulatory/Certification etc teams before the design enters into volume manufacturing. In another context, where the base design (First pass or prototype) is already fabricated and hardware is available for testing and subsequently each of the following test stages may drive one or more changes in the design, before it enters into volume manufacturing: Bring up, characterization, validation, integration, functional, system test, regulatory and manufacturability. All of these different stages may trigger multiple changes to accommodate or enhance the following things in order to make the base design cleaner and stable.


Logic bugs fixing related to functional errors during bring up or functional test


New features addition to accommodate new version of main and peripheral chipsets


Design correction/enhancements from multiple disciplines, say mechanical, electrical and software development


Design correction or fixes for EMI/EMC & UL regulatory compliance


Enhancements to improve usab...