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Placement Algorithm with Deterministic Congestion Intelligence

IP.com Disclosure Number: IPCOM000212386D
Publication Date: 2011-Nov-09
Document File: 4 page(s) / 420K

Publishing Venue

The IP.com Prior Art Database

Abstract

Many VLSI Silicon processes look towards a technology that uses less metal layers to reduce cost. However, the analysis is complicated by the problem of congestion. Congestion is generally realized so late in the design cycle that it impacts the time to market. One step in design cycle where there is a jump in the congestion and area utilization is Clock Tree Synthesis, after which the actual routing scenario may be viewed and which is used to determine the final floor plan. SOC routing is complicated by timing violations near the end of the design cycle. With less opportunity for optimization at this stage, the timely closure of routing and timing is a big challenge. In this paper, we propose a solution that takes the form of a placement algorithm with deterministic congestion intelligence.

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Placement Algorithm with Deterministic Congestion Intelligence

 

Abstract

Many VLSI Silicon processes look towards a technology that uses less metal layers to reduce cost.  However, the analysis is complicated by the problem of congestion.  Congestion is generally realized so late in the design cycle that it impacts the time to market.  One step in design cycle where there is a jump in the congestion and area utilization is Clock Tree Synthesis, after which the actual routing scenario may be viewed and which is used to determine the final floor plan.  SOC routing is complicated by timing violations near the end of the design cycle.  With less opportunity for optimization at this stage, the timely closure of routing and timing is a big challenge.  In this paper, we propose a solution that takes the form of a placement algorithm with deterministic congestion intelligence.

The placement algorithm may be used to estimate a jump in area utilization and hence,  congestion, prior to layout.  This information allows not only for improvements in placement and optimization, but also in making significant early decisions for floor plan closure.

General SOC Flow  

               

Figure 1: General SOC closure flow

Figure 1 show the general flow adopted for SOC design closure.

Understanding the Congestion Problem

Figure 2 is illustrates an SOC design process from the placement stage, at which timing closed, to the Clock Tree Synthesis (CTS) stage.  The timing closed design was optimized with low utilization.  After CTS, we can see that many clock buffers have been added to the design, and these clock buffers have special routing rules like double/triple spacing.  With this design, metal track utilization is very high, resulting in local congestion and hot spots.  The clock tree cells inserted during CTS are shown in red.   The congestion and hot spots impact post-CTS routing.  The problem is even more pronounced in four metal layer designs where the base metal layer is used by standard cells and the top, thick metal layer is used for power routing, leaving only two metal layers left for routing.

Figure 2: Congestion after Clock Tree Synthesis

Special Clock Tree Routing Rule

Clock tree cells are routed with special routing rules that consume extra routing space to avoid the effects of noise on the clock nets.  There are two main types of clock net routing rules, DWDS (double width double space) and SWTS (single width triple space), both of which occupy more space than data nets.  Figure 3 shows a comparison of a data net vs. a clock net.

        

Figure 3: Congestion introduced by clock net routing

Clock tree cell insertion and special routing rules for clock nets together can introduce excessive congestion in the design very late in the design cycle and can lead to net detouring, causing timing violations.  It also may introduce floor plan changes.  The scope for data path optimization also is reduced at this stag...