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Method and System for Forming Dual Stress Liners Disclosure Number: IPCOM000212477D
Publication Date: 2011-Nov-15
Document File: 5 page(s) / 177K

Publishing Venue

The Prior Art Database


A method and system for forming dual stress liners is disclosed. The method uses two stress liners, one with small lattice constant and the other with large lattice constant, to fabricate a semiconductor wafer.

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Method and System for Forming Dual Stress Liners

Disclosed is a method and system for forming dual stress liners. The method uses existing "dummy gate" regions in a Replacement Metal Gate (RMG) process flow. The dummy gates may exist over the active (RX) regions or over the Shallow Trench Isolation (STI) regions of a semiconductor wafer. Selective etching of the dummy gates and etching through the opening into the STI may be performed to form a trench. The trench may be filled with stress liner material which may be an insulator with compressive or tensile strain. The method is performed separately for the dummy gates surrounding the N Field Effect Transistors (NFETs) and dummy gates surrounding the P Field Effect Transistors (PFETs). The excess stressor material is thereafter planarized.

Initially, an Interlayer Dielectric (ILD) is deposited on the CMOS device and thereafter, the deposited ILD layer is planarized. The devices used in the disclosed method may use bulk or SOI substrates.

Fig. 1 illustrates the initial stage of the fabrication process where silicon substrate is represented in red and trench isolation region in light blue. As shown in fig. 1, sidewall spacer edge and RX/STI edge coincide. An alternate embodiment would have the sidewall spacer overlap the STI edge, such that the dummy gate edge coincides with the STI edge (Fig. 2).

Figure 1

Fig. 2 illustrates the second step of the fabrication process where an etch mask is formed over the dummy gates. A compressive liner is then formed and the opening formed by the etch mask is kept large in order to expose the dummy gate stack. However, a sufficiently large opening may expose ILD and subject the exposed ILD region to subsequent etching. Consequently, the etch mask opening is optimized in such a manner that the opening becomes sufficient for etching out targeted material and for supporting the alignment tolerance determined by the length of the spacer material along the dummy gate sidewalls.


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Figure 2

Fig. 3 illustrates the third step of the fabrication process where the exposed cap material and dummy gate stacks are selectively etched away. As shown in fig 3, an anisotropic Reactive Ion Etching (RIE) is performed to form a local trench within STI regions. The maximum etch depth is determined based on efficiency of re-filling the trench region with stressor material. The depth of etch may also depend on lattice mismatch between the stressor material and adjacent substrate. If the mismatch is large, the trench etch depth may be kept small in order to facilitate improved re-filling of the trench region without significantly impacting channel strain. Thereafter, the etch mask is removed and the trenches are filled with a compressive stress liner, shown as topmost blue region. Since, NMOS devices traditionally require tensile stressors, a compressive material having smaller lattice constant than the adjacent active region may be used for NMOS devices.