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System and Method for Automatic Insertion of Partial Good Test

IP.com Disclosure Number: IPCOM000213184D
Publication Date: 2011-Dec-07
Document File: 7 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a system and method for the automatic insertion of a Partial Good Test during the development of very large semiconductor chips. This approach greatly simplifies the insertion of the test structures necessary to isolate redundant structures, making development of very large chips much more cost effective.

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System and Method for Automatic Insertion of Partial Good Test

It is cost prohibitive to produce very large semiconductor chips due to decreased yield from increased amounts of logic and wiring. On chips that have redundant logic structures, a method of isolating the testing of these structures and marking some unusable can result in substantial increase in yield. However, so far the difficulty in development of testing structures for the isolation of these structures has prevented the use of a "partial good test" solution for many large chips.

The partial good test method greatly simplifies the insertion of the test structures necessary to isolate redundant structures, making development of very large chips much more cost effective. Rather than having a custom implementation for each chip, this method provides a means of inserting isolating test logic on any chip with redundant logic structures.

This invention includes the automatic processing of elements that have been identified as redundant. In this processing, test structures are inserted to isolate redundant logic and steer test related signals such that the redundant elements can be individually accessed during test, allowing them to be identified as "good" or "bad" as the result of Automatic Test Pattern Generation (ATPG) testing.

Definitions:


PGT - Partial Good Test
PUPGT - Part/Core/RLM Under Partial Good Test
BSL (Boundary Scan Latch) - A latch that isolates every port of PUPGT
BSC (Boundary Scan Chain) - BSLs daisy chained to create BSC.

SGL (Scan Gated Latch) - Optional Latches on a separate scan gate to prevent their reading during in system scan
SGLC (Scan Gated Latch Chain) - SGLs daisy chained to create SGLC
ISC (Internal Scan Chain) - Formed by all other latches in PUPGT including SGLs but not BSLs
OPMISR - On Product Multiple Input Signature Register

This methodology is dynamic and can be implemented into any given chip with redundant logic circuits. It uses multiplexors and a few other primitive gates to isolate the target core from the rest of the chip. Each PUPGT has three distinct scan chains: Internal, Boundary, and Scan Gated, and three different test modes: Level Sensitive Scan Design (LSSD) (Normal), Partial Good Test and Bypass.

Design requirement -

PUPGT needs to be isolated from the rest of the chip with latches. This is accomplished by latching each port of PUPGT using BSLs. These latches are daisy-chained to form Boundary Scan Chain for PUPGT.

Steps:

1


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1. Determine PUPGT group size: Based on the total number of PUPGT in the design, determine the required number of PGT groups and the optimum number of scan chains in the group.

Algorithms:
Num_of_group** = total_num_of_PUPGT/max_available_scan_chains Optimum_num_of_chains** = total_num_of_PUPGT/ Num_of_group** Size_of_group_select_mux = Num_of_group + 1


** If the quotient is not integer take the next higher integer number.

In the instance of having 100 Parts for PGT and 31 available scan chains...