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Method of forming a SRAM antifuse

IP.com Disclosure Number: IPCOM000213585D
Publication Date: 2011-Dec-21
Document File: 3 page(s) / 40K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of forming a Standard Random-Access Memory (SRAM) antifuse as related to electrical antifuses used in integrated circuit chips. The invention provides an alternative smaller size which is a scalable and more cost-effective eFUSE solution to those commonly used in current technologies and products. The essence of this invention is to realize the function of an antifuse, a non-volatile memory with modified standard volatile memory in Complimentary Metal-Oxide Semiconductor (CMOS) process.

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Method of forming a SRAM antifuse

This invention provides a cost-effective eFUSE solution in a Complimentary Metal-Oxide Semiconductor (CMOS) technology. Using the standard volatile memory cell, Static Random-Access Memory (SRAM), the invention introduces an extra pull-up device to one side of the cell that intentionally destroys the ability of writing "0" into it. As such, all cells initially have a fixed "1" stored into them. The approach introduces a programming mechanism into the extra pull-up device which can sever it from the original standard cell with the application of a voltage of about 2.0 volt. Once the extra pull-up device is severed, the modified SRAM cell returns to a standard cell (i.e., a "0" can now be written into it), and thus accomplishes the function of an antifuse: namely, write "0" into
a cell and it reads out as "1" for an intact fuse and as "0" for a programmed fuse.

The invention consists of modifying the standard SRAM cell through the addition of an extra pull-up device on one side of the cell. The extra device intentionally destroys the ability of the cell to write "0" into it and as such, all cells will always read back with "1" stored in them.

A programming mechanism is further introduced into the extra pull-up (PU) device such that upon application of a voltage pulse of about 2.0-2.5 volt for about ~10-100 ms, this device is disabled and the modified cell becomes the original standard SRAM cell. The programmed cell thus reads back a "0" after a "0" is written in, as compared to the un-programmed or intact cell that will read back a "1" after a "0" is written in.

With this invention, a portion of the standard SRAM memory block can be modified to realize the function of eFUSE and as such no other stand-alone eFUSE solution as used in today's technologies is needed.

The advantages of this invention include a small area, ~0.3um2 cell size vs. current ~ 8um2 for the 32nm technology node. In addition, a hot-carrier (HC) programming mechanism is used here, vs. the electromigration (EM) in standard eFUSE solutions; thus, no large programming current is needed, eliminating the need for complicated circuit design and current delivery system. Finally...