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ACCELERATION OF FAULT INJECTION SIMULATIONS

IP.com Disclosure Number: IPCOM000214415D
Publication Date: 2012-Jan-26
Document File: 4 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Related People

Adrian Evans: AUTHOR

Abstract

Using a cyclic redundancy check (CRC) or other checksum, the state of a device under test in a fault injection simulation can be quickly compared with that of a golden simulation. This quick comparison makes it possible to immediately terminate the fault simulation. Since most faults are over-written, with this technique, most fault injection simulation runs are highly accelerated and often can be terminated after a small number of clock cycles.

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ACCELERATION OF FAULT INJECTION SIMULATIONS

AUTHORS:

Adrian Evans

CISCO SYSTEMS, INC.

ABSTRACT

    Using a cyclic redundancy check (CRC) or other checksum, the state of a device under test in a fault injection simulation can be quickly compared with that of a golden simulation. This quick comparison makes it possible to immediately terminate the fault simulation. Since most faults are over-written, with this technique, most fault injection simulation runs are highly accelerated and often can be terminated after a small number of clock cycles.

DETAILED DESCRIPTION

    Silicon systems increasingly need to be tolerant of faults - both soft and hard- errors. Fault injection simulations are the primary method to evaluate the susceptibility
of a system to a given class of faults (e.g., sequential soft-errors, combinatorial soft-errors, timing-faults, etc.). The purpose of such simulations is to identify the effects of faults when the system is operating in the field. If the likely effect of faults precludes achieving system reliability targets, then mitigation techniques such as parity, triple-modular redundancy (TMR), etc., are required. Using the results of fault injection simulations, it is possible to identify the most susceptible regions of a circuit in order to implement selective mitigation.

    The problem with fault injection simulations is that they are computationally intensive as the number of possible faults is quite large. Integrated circuits can have as many as 10 million flip-flops or more, and it may be necessary to inject multiple faults for each flip-flop in order to determine the susceptibility of a node at different points in time and in different operating modes. A typical functional simulation can take between

Copyright 2012 Cisco Systems, Inc. 1


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10 minutes to an hour to run. Without acceleration techniques, it is not practical to run exhaustive fault simulations on designs with millions of flip-flops.

    Accordingly, an innovative and practical approach is provided for accelerating fault injection simulations that can achieve an order of magnitude of improvement in simulation throughput.

    It is well known that a large number of faults (typically 70-90%) do not propagate. One possibility is that the corrupted state from the fault is not stored in any downstream flip-flops (or memories) because it is not selected through the combinatorial logic. In this case, in the clock cycle after the fault, the circuit has returned to its original (or golden) state, as if no fault had occurred. Another possibility is that the corrupted state does propagate to one or several downstream flip-flops but that after some number of clock cycles, this corrupted state is overwritten and then the state of the device under test (DUT) returns to the golden state.

    A key to accelerated fault injection simulation is to avoid repeated simulation of the same stimulus. Use of standard check-point and restore techniques make it possible to start a f...