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Modeling logic overhead cost.

IP.com Disclosure Number: IPCOM000215270D
Publication Date: 2012-Feb-23
Document File: 2 page(s) / 28K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for modeling logic which would be added during later steps. The a snapshot of that logic is created and applied to future iterations. This enables earlier steps in a methodology to see a more accurate view of the final result than they would otherwise be able to see.

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Modeling logic overhead cost .

When doing placement driven synthesis of digital logic, designers commonly encounter the problem that not all logic is contained in the netlist being synthesized. Some logic for test purposes may be added later by front-end processing tools. Additional logic may be added for clocking or other purposes. The area and wire resource needed by this logic will not be modeled in the synthesis work that is done before these processing steps.

    One common solution is to use placement blockage shapes which prevent any logic being placed in the areas where the additional logic may be placed. This has the drawback of being inaccurate. It may not model the blockage in the correct location and does not model the wiring resource needed.

    The core of the invention is to mark the logic added by front-end processing or other tools with keywords when it is added. After placing and optimizing all the gates, all the logic which has not been marked with the keyword is pruned away and the remaining logic is saved as a 'test logic snapshot.' This snapshot is used as a placeholder in future synthesis iterations to reserve the area and wire resources needed..

    This method has the advantage of providing a more accurate representation of the locations where the test logic will be placed and modeling some (although not all) of the routing demand from the nets connected to this logic.

    This description shows front-end processing tools as an example, but the technique could apply to other areas such as clock insertion. The disclosed process follows the flow shown in the figure below.

1) First synthesize the logic to create a gate level netlist. Initially, this needs to be done without a test logic snapshot as the snapshot would not exist yet.
2) Add test logic to the netlist using existing front-end processing tools.


3) Annotate all of the added test logic with keywords.

4) Run placement and timing optimization tools on the ne...