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Method and System for Dynamically Controlling Speed of Memory Bus based on Power Available in a System and Prioritization of a Workload

IP.com Disclosure Number: IPCOM000215886D
Publication Date: 2012-Mar-14
Document File: 1 page(s) / 21K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for dynamically controlling speed of memory bus based on power available in a system and prioritization of a workload.

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Method and System for Dynamically Controlling Speed of Memory Bus based on Power Available in a System and Prioritization of a Workload

Disclosed is a method and system for dynamically controlling speed of memory bus based on power available in a system and prioritization of a workload. The speed of memory bus is automatically adjusted based on signal from a power subsystem. The signal from the power subsystem includes details of availability of power to support higher speed of memory bus. The system determines the availability of power regardless of system configuration by monitoring precision analog or digital signal from the power subsystem.

In multi-socket systems, each memory bus of each core runs at different speeds. Lower priority workloads can be assigned to certain cores and the speed of each memory bus can be scaled back to reduce power consumption. High priority workloads can be assigned to dedicated cores which run memory bus at highest possible speed to ensure maximum performance.

In an instance, a server can be designed such that a hypervisor may select workloads to be run based on prioritization profile. The prioritization profile may be included in virtual hardware profile created by a virtual machine. By combining a hardware mechanism with software mechanism, system power can be saved. The hardware mechanism controls the speed of memory bus and memory mapping with software mechanism allocated "pin" memory for specific workloads or virtual machin...