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Maximizing Decoupling Capacitance Utilizing Fill

IP.com Disclosure Number: IPCOM000216024D
Publication Date: 2012-Mar-19
Document File: 8 page(s) / 159K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is an invention on how to take advantage of the existing metal fill process that occurs post design but prefabrication to improve manufacturability through increased decoupling capacitance in the BEOL metal stack.

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Maximizing Decoupling Capacitance Utilizing Fill

As chips become smaller, there is less room in the chip floor plan for regions of decoupling capacitance. This is due to non-linear scaling of all units resulting in a condensed chip size as there is less available white space where decoupling capacitance is usually placed. Furthermore, when adding decoupling capacitance, it requires the use of white space not utilized by the chip's functionality requirements, thus causing a trade-off of expanding the overall unit and/or chip size for more decoupling capacitance. Additionally, there may be critical circuits requiring close proximity to decoupling capacitance which may need to be added to the net post design where the most cost effective solution is to maintain BEOL changes only. Also, with recent changes in 22nm technology that reduce the amount of capacitance in the typical technology capacitor device, it would be advantageous to have a method to replace the lost amount of capacitance without having to change the design floor plan to add additional decoupling capacitor devices.

    The solution to the above problem is to take advantage of the existing metal fill process that occurs post-design but prefabrication to improve manufacturability. Currently, the fill process just adds floating metal fill where possible to not create any physical errors, such as DRC/LVS errors. This invention would enhance the fill process by tying (adding vias) adjacent fill regions to either VDD or GND based on its nearest neighbor's wire connection to VDD or GND to create decoupling capacitance in the metal planes. The fill regions are wasted space from a designers perspective, so it is beneficial if this dead space can be featured to improve the overall functionality of the chip. Thus, the tied fill areas to the power rails would aid the design as well as manufacturing.

This invention of maximizing decoupling capacitance by utilizing fill shapes to increase the connections and surface area of the VDD, GND, or other power grids. First, a fill tool will be used to identify areas metal can be added. A labeling process will then be used to mark the new fill shapes with the proper power rail label. Echk can then be used to identify where vias can be used to connect the fill shape with the correct power rail. Finally, a missing vias tool is used to create the vias and connect the fill shapes with the correct power rail. This will add extra decoupling capacitance to the chip without increasing the floor-planned decoupling capacitor space set aside during FEOL design activities.

    Methodology - Utili...