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Output switch arrangement for Functional Safety and Robustness during System level stress

IP.com Disclosure Number: IPCOM000216042D
Publication Date: 2012-Mar-20
Document File: 2 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

An emerging requirement for Integrated Circuits in the automotive domain is to guarantee the IC can reach high level of safety (Asil-D) and robustness (Class A ISO10605, IEC61000-4-2 ) : a circuit has to operate normally (no reset for instance) during and after system level stress such as ESD gun. No IC manufacturers guarantee the normal operation of an IC during system level stress (ESD) due to design constraints and test difficulties. Usually it is addressed at the application or system level. This publication shows an output arrangement to reach this goal at the IC level on active low pins, like Resetb or safety pins: the pull down transistor is connected in such a way that the pin is maintained high (no fault reported) whatever the level of the ESD stress.

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Document Title 

Output switch arrangement for Functional Safety and Robustness during System level stress

   

Abstract 

An emerging requirement for Integrated Circuits in the automotive domain is to guarantee the IC can reach high level of safety (Asil-D) and robustness (Class A ISO10605, IEC61000-4-2 ) : a circuit has to operate normally (no reset for instance) during and after system level stress such as ESD gun. No IC manufacturers guarantee the normal operation of an IC during system level stress (ESD) due to design constraints and test difficulties. Usually it is addressed at the application or system level.

This publication shows an output arrangement to reach this goal at the IC level on active low pins, like Resetb or safety pins: the pull down transistor is connected in such a way that the pin is maintained high (no fault reported) whatever the level of the ESD stress.

Body 

In safety-relevant applications in the automotive area (related to ASIL-D / ISO26262), it is required to guarantee a robust operation during and after system level stress such as ESD gun.

A solution consists in preventing the turn-on of an output switch during an ESD event and is described hereafter. While an ESD stress is applied on a pin during normal operation of the IC, the current into the substrate can reach tens of Amperes. The rising of the substrate voltage into the IC can cause the turn-on of a NMOS pull down transistor, driving an active low pin like RESETB pin. This is due to a substrate diode connected at the gate : this parasitic diode may be added in the circuit by the isolation connec...