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A novel approach to routing congestion mitigation with local box movement

IP.com Disclosure Number: IPCOM000216279D
Publication Date: 2012-Mar-28
Document File: 6 page(s) / 132K

Publishing Venue

The IP.com Prior Art Database

Abstract

As the technology node continues to shrink and VLSI industry tries to keep up with Moore’s Law, routing congestion has become one of the major problems in the Chip Design flow. Routing Congestion also leads to long run time of the Detail router, Scenic wiring , Timing violations, electrical violations, DRC violations, and longer overall TAT .Thus Routing Congestion needs to be addressed at various stages of the design process. The CBOX_MOVE method described here tries to solve the routing congestion problem by moving the cells from the routing congested regions to other lesser congested regions.

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A novel approach to routing congestion mitigation with local box movement
In the VLSI Chip Design flow, placement of the cells has to lead to both timing and routing closure. Timing closure and Routing closure both are of equal priority. Routing congestion during placement stages has to be analyzed and mitigated. The method described below addresses this problem at placement stages.

It is assumed that the initial placement of the cells is done and a first pass of global routing has been run on the design.

The method described here selects the Cells in the congested region and moves them to a legal location which is relatively less congested. The movement of the cells is incremental and the incremental global routing is run once the cells are moved to a legal location to measure the new congestion. Incremental timing is also utilized to compute the effect on timing and ensure that no new timing/electrical violations are introduced. This is implemented using the MAR Global Router, Synthesis congestion Interface (SCI) , IMAP , MAR Incremental Global Routing, Incremental timing subsystem, and the core algorithm is CBOX_MOVE .

BRIEF SUMMARY OF THE INVENTION

It is assumed that the initial placement of the cells is done and a first pass of global routing has been run on the design.

The method described here selects the Cells in the congested region and moves them to a legal location which is relatively less congested. The movement of the cells is incremental and the incremental global routing is run once the cells are moved to a legal location to measure the new congestion. Incremental timing is also utilized to compute the effect on timing and ensure that no new timing/electrical violations are introduced. This is implemented using the MAR Global Router, Synthesis congestion Interface (SCI) , IMAP , MAR Incremental Global Routing, Incremental timing subsystem, and the core algorithm is CBOX_MOVE .

DETAILED DESCRIPTION OF THE INVENTION

Global router divides the chip image using a tile/grid into cells called Gcells for each routing layer. For each Gcell edge on a layer, a capacity is computed based on the

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number of routing tracks available for nets crossing that edge. Once global router creates global routes, the actual number of nets crossing a particular edge may be
computed. If such number of nets crossing a particular edge exceed a threshold such as, say, utilizing 90% of the capacity computed for that edge, then such an

edge is considered congested. Any net crossing a congested edge is considered a

congested net.

It is assumed that the design is already placed .A first pass of the global router is run. We compute the timing of the design before any cell is moved from the current location.

Let Congested edge cost for a global routed net : CEC(net) be the total number of congested Gcell edges crossed by the net. Let the Congested edge cost for a target box : CEC(box) be the sum of the CEC of all the nets connected to the...