Apparatus for Front Edge Wordline Repowering in Large Arrays Via a Distribute Pull-Up
Publication Date: 2012-Apr-02
The IP.com Prior Art Database
Described is an apparatus for front edge wordline repowering in large arrays via a distribute pull-up.
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Apparatus for Front Edge Wordline Repowering in Large Arrays Via a Distribute Pull-
As we continue to scale to smaller and smaller gate lengths, the need to locally repower the wordline (WL) and precharge signals in large custom arrays has increased. The reason for this is that while we have been able to continue scaling the devices themselves, the resistance of the wires has not scaled accordingly. The increased resistance in the wires has caused the RC delays on the wordline and precharge signals that control the access of the array cell itself to become too large.
One common solution for this problem is to insert local inverters midway across the array to refresh the signal. The problem with this implementation is that you are not only adding extra area to the array itself, via the buffer and extra edge cells, but also inserting at least two stages of delay between the near and far end of the wire which slows down access time. An alternative approach is to repower only the front edge of the WL and precharge signal via a distributed pull-up device. The reason that only the front edge of the wordline or precharge signal would need to be refreshed is that the falling edge of those signals does not affect the access time of the array. Often larger arrays operate in frequency domains where the time between the wordline or precharge signal falling to the next signal rising is large enough that a large slew can be tolerated.
The distributed pull-up scheme consists of a single pfet device that is placed at various intervals across the array and is driven by the output of the second to last stage of the wordline or precharge driver. By driving the distributed pull-up device with the output of the second to last stage, you are affectively boosting the repowering points of the wire before the actual signal arrives. This greatly reduces the RC delay on the front edge of the signal while inserting a minimal number of devices into the array core itself. This approach could also be expanded to add a distributed nfet to help with the falling edge as long as the RC delay of the wire driving the distributed devices is less than that of the RC delay of the main wl to the devices themselves.
Figures 1 and 2 below are models of a standard array core with and without a buffering repowering scheme. The array core being modeled is 176 cells wide which is equivalent to an L1 icache on a standard microprocessor. For the buffering repowering scheme, it is assumed that only one repower is necessary and that the buffers are placed midway through the core or 88 cells in. One should also note that the model is looking at the generation of the wordline that controls the access of the SRAM cell itself. This was done for simplicity sake, but this approach is not limited to just the wordline signal. This same approach is applicable to the precharge signal that precharges the local bit lines of the SRAM cell as well as any other long distributed net.